This reverts commit aacf97b953.
Change-Id: I3337457b06ba37da2cfa902e04de367195a4836a
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
Currently, there is a race condition in GenPD framework where
GPU CX GDSC can remain ON if both GMU and KGSL SMMU devices are
suspending in parallel and are voting on the same power domain.
Guidance from genpd team is to use a dedicated power domain for
CX GDSC voting.
Change-Id: Iffeb9a7f24a5e3c31a325e57b021f87f8f94c7fb
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Read the gpu speed bin devicetree property on sun devices.
Change-Id: I54c444bc434a2475ffe5126b7452f642f4dc7b2a
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>
GDSCs were modeled as regulators till now. However,
moving forward, GDSCs will be treated as power domains.
Consequently, replace references to ‘regulators’ with
‘power domains’ for the sun GPU.
Change-Id: I607a511754d56728d5013004d0ae83544f873df6
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Add ACD values for supported voltage levels for Sun GPU.
Change-Id: I8361f4026afbf05ba26860307ffc7158b55b8d2f
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add supporting power levels for AB and AC sku devices.
Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
SVS is the highest voltage corner for GMU. The lowest DDR BW
that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX
at a corner high enough such that GMU can run at 650 MHz. This
is to get better GMU performance at no extra power cost.
Change-Id: I919476577e9b2e69161142c93d47e91505ffc222
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
For gen8 targets, frequency limiter violations are published
through cx_host_irq interrupt. Thus, add cx_host_irq for sun
GPU.
Change-Id: Ie7e0c7fc53bdc002261ee05339c3e4c49da83ea0
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Hardware fence feature requires that we keep soccp from power collapsing
as long as GMU is active.
Change-Id: I3721aefd8cb34edfeba846115132002defa8f385
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
Add device tree nodes for coresight CX and GX DBGC blocks
for sun devices. Also, add coresight funnel configuration
for graphics funnel device.
Change-Id: Id0a73ac9ef51e1039b718d5d51a4fc063d218a94
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
KGSL driver doesn't program PDC registers anymore.
Thus, remove the register information from device
tree for sun GPU.
Change-Id: I60c78e00942bb68e311b4c4632e5a3e2ed30dcd6
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
QDSS clock is used in kgsl to program ISDB registers. Add the clock so
that kgsl can vote for it when needed.
Change-Id: I2b71bdc4b9884409c598ba20759c56bff12cdb64
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Enable Sun GPU to perform graphics functionality.
Also add ipc-core property for hwfences support.
Change-Id: Ia01d92e4b2d43a1f8ec24ff63768aab5d7a4e1e3
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
Add the devicetree files for the GPU on Sun devices.
Change-Id: Iaf7a19eb5e2c6c215e838ae1bfa3b01916c804d9
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
