Remove the qcom,cesta-l1sub-timeout-ext-int property as its no
longer required due to recent changes in the pcie driver using the
change commit b53d4aa20ee7 ("pci: msm: Add support to enable
PCIE CESTA clkreq config").
Initially this property was intended to be used to enable the BIT(3):
PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA
is enabled and the platform is not pineapple.
Currently the pcie driver will by default set this BIT(3) when CESTA is
enabled and the qcom,pcie-clkreq-offset property is present. Since the
qcom,pcie-clkreq-offset property will not be present when CESTA
is enabled on pineapple, pcie driver will not touch the
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register.
Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when
qcom,pcie-clkreq-offset property is present and CESTA is not present
which is the case of pineapple platform when CESTA is enabled. And
this case is also taken care of by the pcie driver without the need
for qcom,pcie-clkreq-offset property.
Below are the required cases that needs to be taken care of by the
pcie driver.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | BIT(0) set | BIT(3) set | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | need to set| need to set| non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | set by | Not | pineapple |
| | default | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | need to | Not | pineapple |
| | unset | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset
property in the following way.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | qcom,pcie-clkreq-offset | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | YES | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | NO | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | YES | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add the device_type property in the pci device tree as a mandatory
property so that the ranges property will be read correctly by
the of framework (of.c) file when pci framework is parsing the
pci device tree nodes.
Also add the qcom,cesta-l1sub-timeout-ext-int property as an
optional property for the platforms that have cesta clkreq routing
bit disabled and legacy l1ss timeout enabled by default.
The presence of this property on a cesta enabled platform will
enable routing of the L1ss timeout interrupt to cesta HW block
instead of routing it to APPS subsystem.
Change-Id: I96db05d6cd38f507c7ddba968ee65808b8263076
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
