dt-bindings: pci: Add pci-msm-msi device bindings

Add devicetree bindings for pcie MSI controller.

Change-Id: I0a049028e40e04dc0c5fd3b16651b1e22f8f757d
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>

bindings/pci/qcom,pcie-msm-msi.yaml

@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-msm-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) MSM PCI express MSI controller
+
+maintainers:
+  - Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
+
+description:
+  Qualcomm Technologies, Inc MSM PCIe MSI controller is based on the
+  Synopsys DesignWare PCIe IP.
+
+properties:
+  compatible:
+    const: qcom,pci-msi
+
+  reg:
+    items:
+      - description: PCIe MSM MSI controller specific registers
+
+  interrupts:
+    maxItems: 32
+
+  msi-controller:
+    description: This is a boolean flag that indicates this is a MSM PCIe
+                 MSI controller node.
+    type: boolean
+
+  qcom,snps:
+    description: Set if interrupt controller is Synopsys instead of QGIC.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+  - interrupt-parent
+  - interrupts
+  - msi-controller
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    pcie0_msi: qcom,pcie0_msi@17110040 {
+        compatible = "qcom,pci-msi";
+        msi-controller;
+        reg = <0x17110040 0x0>;
+        interrupt-parent = <&intc>;
+        interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+            <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+        status = "disabled";
+    };