Modify SMMU register field format as per the parent SoC
address and size cells.
Change-Id: Ifce3e103601a82b1b9f6295d6abef826f917b0fc
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Bring the values in line with hw configuration.
Change-Id: I311222480b2228d12c42c18d21830223759f01a8
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add UI peripherals support for tuna for pmxr2230
and pm7550ba.
While at it add pm7550ba, pmr735b, pmxr2230 files.
Change-Id: If355df7776f21e71e632966d691f13a14a9b3e4f
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Add the secure-buffer device, which supports hypervisor operations
to change the stage 2 permissions of memory.
Change-Id: Ie35729df57e57abba37cf4a286f5f4ac2faa1154
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Configure per-context bank pre-fetch settings using
actlr for tuna.
Change-Id: I9053c5ddac34a25d60fa7345f533678ff294d454
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Enable bus bandwidth voting by adding interconnect properties
for kgsl and apps smmu on tuna.
Change-Id: Iafb8c6975154048aff74b04fad75c9ce0f48aa3e
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Add clock and regulator which would be required for
register accesses of kgsl-smmu for tuna.
Change-Id: Ib09be9911e6b37b1e83ad59183a46284de2835b9
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Add boot_config reg reading support for shdci bootdevice
node through nvmem cell to check if the boot device is
emmc or ufs.
Change-Id: I341de8e37df9c2758889abf7c643b8a66c82f9d9
Signed-off-by: kamasali Satyanarayan <quic_kamasali@quicinc.com>
Update the compatible string of evacc for sun
v2 platform.
Change-Id: I3701aa5031cfb0568f9b8f3cf10e3ec499b270bf
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Add boot_device_type support and flag non-removable
for ufs node to check if the boot device is emmc or ufs.
Remove qcom,ufs-dev-revert to identify ufs device Version.
Change-Id: Id9e925d78860c4518ab10c12cc628dd8b385a5e8
Signed-off-by: kamasali Satyanarayan <quic_kamasali@quicinc.com>
Remove SDPM clock driver support from clarence gaming.
Remove cpu pause action on boot core.
Add cold temperature interrupt handling support in clarence.
Change-Id: I05da43e8a8e392f2bec8f425ac9750f559221953
Signed-off-by: Nitesh Kumar <quic_nitekuma@quicinc.com>
Add support for ice wrapped keys to the MMC DTSI entry
on parrot targets.
Change-Id: Ia818b700bfd2d7f117e90f0d1d1fdc2befe10cce
Signed-off-by: Seshu Madhavi Puppala <quic_spuppala@quicinc.com>
Add the TLMM GPIO reserved ranges for the sdxkova platform.
The reserved range is set to <110 6> to ensure proper
allocation and avoid conflicts with other GPIOs.
Change-Id: I6b01f9c6a21f918df078dcbe078be602dd889898
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Update the compatible string of cambistmclkcc for SUN v2
platform.
Change-Id: I5a984c8ea24308fbe39c4e84e61cc38891e1f7eb
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
Spilt memdump entries to static and dynamic dumps. Static dumps
are enabled by default. Dynamic mem dumps are enabled/disabled
using sysfs nodes and it's disabled in perf build.
Change-Id: I1f1f105d796391ec6e6001c249add9e8ba4b91ce
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Set RX settings mode to zero for Ultrashort channel
settings for sun PCIe controller.
Change-Id: I50b7896e6dabb2cda069c9242340dee02a225b8c
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Add idle states for CPUs and CPU clusters, added PSCI device,
to enable CPUs to enter deeper LPMs.
Disabled the idle states till Rumi validations are done.
Additionally. updated APPS RSC device to be in cluster power domain
to handle RSC activities when cluster is powering off.
Change-Id: I0dc50ff04bb480eb9ebdfa0bbaebfdf954c7c41b
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
The tui_test heap will be used by the large_dmabuf test
on sun-vm.
Change-Id: I84e5aee85c03e2cc809acc307509ce00aa74d967
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
When all clients remove DDR bandwidth vote, DDR may power collapse.
As part of its shutdown sequence, it waits for an 'active' signal to
no longer be asserted by the gpu cx gdsc. Thus, if SW votes for the
gdsc to be active, but not for DDR bandwidth, this sequence may
get stuck.
Change-Id: I48d704f08cfe6d17159eb04d02f5ed123809f967
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
