Add support for ice wrapped keys to the UFS DTSI entry
on sun targets.
Change-Id: I12687b90be6615e38eaeba959c477ac91b2a4377
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Since, we are settle down with 19.2 MHZ for Arch timer frequency
for Sun target, let's do it for VM as well.
Change-Id: I456015fefd6fb7df53cb1d0258e2ee988fd5c88f
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Update disp_rsc device to use correct 0x1000 size instead of 0x10000
for sun.
Change-Id: I81607aaf202ff18032fa117dfbb6f47f4e4ebb40
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Add qcedev crypto support for sun platforms.
Change-Id: Id558a7d0620afa40c8d9b8e43161d8f6ca09e810
Signed-off-by: Daniel Perez-Zoghbi <quic_dperezzo@quicinc.com>
Provide a contiguous region for use by qmc. Unless explicitly
instructed, this region should not be used by external customers.
Change-Id: I98f651c835cf7fa19eba2bc209eb7b7807245877
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
There are some bootargs are redundant and unnecessary getting
carried from older target they are useless and need not be
carried on current targets like service_locator.enable=1.
While some like ftrace_dump_on_oops need to be enable when
minidump gets enabled.
Change-Id: Ib73d1cb7f7e2242dd52524520164c3c89b79083e
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Add the device tree binding for mpm sleep counter
so that it device nodes can be added for respective
SoC where it is supported.
Change-Id: Ic503641c25a4be7121cbf00ccffe103e641cd2f8
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Remove the qcom,cesta-l1sub-timeout-ext-int property as its no
longer required due to recent changes in the pcie driver using the
change commit b53d4aa20ee7 ("pci: msm: Add support to enable
PCIE CESTA clkreq config").
Initially this property was intended to be used to enable the BIT(3):
PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA
is enabled and the platform is not pineapple.
Currently the pcie driver will by default set this BIT(3) when CESTA is
enabled and the qcom,pcie-clkreq-offset property is present. Since the
qcom,pcie-clkreq-offset property will not be present when CESTA
is enabled on pineapple, pcie driver will not touch the
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register.
Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when
qcom,pcie-clkreq-offset property is present and CESTA is not present
which is the case of pineapple platform when CESTA is enabled. And
this case is also taken care of by the pcie driver without the need
for qcom,pcie-clkreq-offset property.
Below are the required cases that needs to be taken care of by the
pcie driver.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | BIT(0) set | BIT(3) set | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | need to set| need to set| non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | set by | Not | pineapple |
| | default | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | need to | Not | pineapple |
| | unset | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset
property in the following way.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | qcom,pcie-clkreq-offset | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | YES | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | NO | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | YES | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This reverts commit 704e2e0186.
Reason for revert: No longer needed once 1ns frequency is disabled.
Change-Id: I2355fff08acf5746efdce7562df99f83bba4696b
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
EUD node was set to bypass the pdc since the pdc node was unavailable.
Now that it's available, set the interrupt parent to the pdc and adjust
the EUD node accordingly.
Change-Id: I2516315753a3452d66b9cad3e6bdc089bb8dcd6c
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
PMK8550 has a couple of high resolution PWM channels which can support
from 8-bit to 15-bit PWM. Add it.
Change-Id: I277bca101546de07ffc8bb34380fc8bbdea10a92
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Updating build files with ATP platform DT support on Sun SoC.
Change-Id: I6e0d614d5ea3c6d781c432e8e5dde900aa1aa02f
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
The qcom,display heap is used for camera usecases.
Change-Id: Ib937670c33284fb2dc624258fd8e5978b4405ace
Signed-off-by: Vijay Kumar Tumati <vtumati@quicinc.com>
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
After hotplugging in memory, automatically online it to the movable zone.
Change-Id: I1dde15451e78196fc261c0bd9b25cdfa91749c4c
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
