With commit (851140def4: Allow memory from lower 4G for adsp/cdsp/modem)
We were limiting addresses to below 4GB for ADSP/CDSP metadata passed to
TZ. The issue with S1/S2 mapping is caused by a flag in the hyp config
file, removing the restriction for ADSP/CDSP metadata memory.
Change-Id: Id42350a8ab2ddff3c74104f610d83a70681c23c6
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Corrected/rectified dma nodes for qup2 i3c instances,
and also added ibi-controller id changes.
Change-Id: I2bbc7391fce38c231c57327547573e0de0d774c0
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
In pinctrl file there is extra space in function name for
qup1_se0_l1, which is leading to ios lines not in good state.
To solve the removed extra space.
Change-Id: I79b34f15bcf3eb52ac950876b3339c77d036983d
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
Disable tpdm pcie-rscc and spss because some related clk can not
be enabled from kernel side.
Change-Id: I17d393c5ccf757198632eba15f133aae0182a05e
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Set the proper EUD UTMI switch delay for when EUD moves between modes.
This allows for the delay to be decreased, which addresses USB core soft
reset timeouts.
Change-Id: Id3f02ad4f14b68977baa3393c692360a762b0ee2
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Sun boards that utilize the V8 power grid have a PM8550VE PMIC in
place of a PM8550VS one for the "F" PMIC at SPMI SID=5. Several
FTSMPS regulators are ganged together differently and some supplies
are shuffled around. These are the impacts for RPMh managed
regulator resources:
V6 Power Grid V8 Power Grid
S4J WCN_CX XX
S5F XX WCN_CX
S6F VDD_MXA XX
S8F N/A VDD_MXA
Update the device tree configurations for V8-specific overlays so
that the correct set of PMIC resources is present.
Change-Id: I035b8dfc87703b7681110a757952005bbdbf8a63
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add a PMIC PM8550VE_F device along with its peripheral device
subnodes. This PMIC is found on Sun boards that use the V8
power grid instead of PMIC PM8550VS_F.
Change-Id: Idf4de30a6ceb891f563341bad0e0da21dca38b69
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add modem related thermal sensors and mitigation devices for sun which
would be accessible over QMI. Add respective thermal zone and trips
for modem thermal sensors.
Change-Id: Iefef9a70d8c213a406d7eb98df43c61f46fddd87
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Add the device nodes on sun oemvm and vm to enable qmsgq socket
communication over gunyah message queues.
Change-Id: Ib28b1204006819ef9fe044586dbaada64d826b4a
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Update bootargs for Sun SoC to align with existing SoCs.
Change-Id: I50c16ddabc4559b84f815d10956c36b63dbafd00
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Enable the qrtr gunyah transport for sun. This enables the QRTR
Gunyah transport on the primary VM which kickstarts the qrtr protocal
between tuivm and pvm.
Change-Id: I6cc9d73d087107de9153a781aea255a077f8ee0c
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Find my device (FMD) feature uses SDAM offset 0x9a for enabling
or disabling the feature in Sun platforms. Add the configuration
to support it.
Change-Id: I76cd1cc8146cdf08af544db474637858ab88211e
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Update scm node to include dload-mode register needed
to set the proper download mode.
Change-Id: I2f2075ec43f1ba452fff6077685afcf6dc7912be
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Add SS phy and HS phy related irqs to sun.
Change-Id: I8f5ae4d8a11434141deb429621225448aac76786
Signed-off-by: Elson Roy Serrao <quic_eserrao@quicinc.com>
To support cable detection events from UCSI, updates need to be made to
enable usb role switch and setting up a connection to the UCSI PMIC glink
node.
Change-Id: Ib7b212ab00022ee4e559f046dddead7aaf7539af
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Update the pcie BAR address in ranges property for sun.
ADSP subsystem is not having access to the previously given
(0x60300000) memory region. So, moving to the lower memory
region to avoid NOC errors for adsp.
Change-Id: Id8223a78cf13d8f2c83095de30b193e85da6829d
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
The gx_clkctl_gx_gdsc requires both gpu_cc_cx_gdsc and VDD_GX to access
its configuration registers. We access these registers during probe, so
we need to ensure these dependencies aren't disabled until after our
probe completes. Add proxy consumers for this.
After probe, the parent-supply will ensure VDD_GX is enabled before we
touch registers in the regulator_enable/disable paths. And for the CX
GDSC dependency, the client already enables it before the GX GDSC due to
historical functional requirements between the CX and GX sides.
Change-Id: I49f5654a8a86644074c76788de821eb8ae621d09
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Enable core etm related components and some TPDMs and CTIs.
Change-Id: I1d7a581a9aad1bc4486685ae9b25a3323c53811d
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
The L1F regulator is a parent for the M31 EUSB2 PHY. Vote for this
regulator when PHY is resumed, and disable when suspended.
Change-Id: I91d309b5afefc7c9b4205e9e73b3714963d3f45f
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Add the REFGEN_VDD_A_0P9/VDD_A_PCIE_0_0P9 regulator so that the
ufs phy driver can vote for this regulator. This vote is needed
according to the Sun's Power Grid Analysis document.
Change-Id: I3427e2f529ec734983ea6c2db97411c997260bb0
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add device tree support for v8 Power Grid on QRD SKU2
platform for Sun SoC.
Change-Id: I4bc070e9dbddae39d033fbf16f5ca811295efff6
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add device tree support for v8 Power Grid with Kiwi on MTP, CDP
platforms for Sun SoC.
Change-Id: I517f023e516cab8735bdd2e264e8028a4e7debe7
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
