Add compatible string to schgm-flash DT node. This was removed
from the bulk DT porting for Ravelin on qcom-6.6 device-tree branch.
Change-Id: I16d410ce8cc15278b0d8a3480a1e7fd5a044669f
Signed-off-by: Shilpa Suresh <quic_c_sbsure@quicinc.com>
This change will add usb-role-switch and eud in Kera.
Change-Id: I74ca8c0e19b45d925bcecc78e993439441339e20
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
To support cable detection events from UCSI, updates need to be made
to enable usb role switch and setting up a connection to the UCSI PMIC
glink node.
Change-Id: Ic3a848f882072a766b3efb872f943dd3f4220ba1
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
DWC3 host and XHCI plat now communicates the maximum number of interrupters
the XHCI HCD will allocate. Since platforms only require a limited number
of interrupters (i.e. 3) make sure XHCI doesn't allocate more than is
required.
Change-Id: I466748df07aba6d7bdc79c7b2b17b3a57c58d3d4
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
During Airplane mode testing with BT, UWB and PCIE concurrent
test scenarios, due to pcie traffic signal tolerance issue seen
on q2spi signals. As per the recommendation from design team
decreasing current drive strength from 6mA to 4mA for q2spi
active state GPIO configuration.
Change-Id: I530dfd636e834c4d6eb1e067e8dcb76dcfa4ab87
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Enable QoS programming for kera and add necessary AXI and
AHB clock handles for programming QoS for USB, IPA and PCIE masters.
Change-Id: I51bcc6a841005b6daf8ab3f22a79e6704dc3b3ed
Signed-off-by: Swetha Chintavatla <quic_chintava@quicinc.com>
Add USB AXI clock handle for accessing USB QoS register to program QoS.
Change-Id: I4e0a0057e55283578ab6333f0da1b46c36e01fe5
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Provide separate file for SLT so that ABL can pick
it properly. Currently, ABL doesn't check if multiple
board-id is added.
Change-Id: I9140ca7b19f6b0b368798950145abbe28e32e778
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Add support for cpufreq_hw and cpufreq_hw_debug nodes on kera platform.
While at it, set the default governor to performance on kera platform.
Change-Id: Id6fd146d3c80f686780591e5efa594bd76155bcd
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Mark the pcie_1 clocks as protected and remove the pcie_1 gdsc
nodes.
Change-Id: I3102a52895a6531fb82a411bdb760073fc3c28f3
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
Mark gpucc clock node as GenPD provider and disable the
graphics GDSC regulator nodes.
While at it, keep the gdsc's as it is on rumi platform.
Change-Id: I91b4915723e26685e950de3ae575540ac3940036
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
Currently, the node for eusb2_phy0 is defined but not used by controller
which makes the associated resources to be consumed. Therefore if phy
probes doesn't happen the controller goes into core soft reset failure.
Fix this by utilizing the node in the controller. This will call the
phy's probe and hence clocks & regulators will be initialized.
Change-Id: Ica46af01154d5e583e011e4f2d84a80fb0589ac8
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
