Increase the number of pipe clock toggles that will occur after
phystatus goes high at the output of the PHY during L1SS/P2 entry
in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and
controller goes out of sync this may help us. The number of pipe
clock toggles is equal to (4*value)+1.
Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Set RX settings mode to zero for Ultrashort channel
settings for sun PCIe controller.
Change-Id: I50b7896e6dabb2cda069c9242340dee02a225b8c
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
No need to configure the SLV_ADDR_SPACE_SIZE register value
from devicetree node because the PCIe driver is taking care
of configure it to the maximum possible size.
Change-Id: I925b51a913be06d14c62ce65a954cdb0d96a814f
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This reverts commit 9ff494b311.
Facing issue where PCIe PHY GDSC is getting turned off when system
suspend is happening. So reverting this change till we find a fix.
Change-Id: I7ea0393f3948a49d8eb012ee548d200f040badd6
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add the list of PCIe SM registers that need to be dumped
to the PCIe dt node in sun.
Change-Id: Ic2e0518ac611ef5e409f88dcd0f69eb2ce4d8566
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Update pcie phy settings for sun to version 94.
Change-Id: I5af8d79cecba0ee1088f379b0d823f3a841e8420
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Replace the PCIe phy gdsc handler with GenPD based PCIe phy
regulator handler to the pcie devicetree node in sun.
Change-Id: I3710e1d90cfd1387e3ac41a5b76bebb5b61d80ba
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Enable PCIe CESTA based drv functionality for sun platform.
Change-Id: I601398b92f7d7d28956573dd413548aaf7716340
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
PCIe CESTA related dtsi node properties and cesta
based is not yet enabled.
Change-Id: I5846df725b690d95ef54ec5f7b85cbe1fe206325
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Update the pcie BAR address in ranges property for sun.
ADSP subsystem is not having access to the previously given
(0x60300000) memory region. So, moving to the lower memory
region to avoid NOC errors for adsp.
Change-Id: Id8223a78cf13d8f2c83095de30b193e85da6829d
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add the qref regulator for pcie node in sun.
Change-Id: I8959a683a5d73429069cd6795f00a5b1fe91c082
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Change the pcie devicetree node names to be in line with the
pci-bus.yaml format.
Change-Id: I46b56b7aee492c746554ac2a3575cd11c2108efb
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Disable software DRV (L1SS sleep) with PCIe instance
on sun platform as ADSP subsystem (software DRV component)
doesn't support this functionality.
Only CESTA based hardware DRV is supported.
Change-Id: I75368fab37e8bcaaa3c65320b6fdd37e023d3297
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add the missing phy gdsc node in the pcie dt node for sun.
Change-Id: I0257c6123d4d3e8fe2740569bd4def68fa3c92a8
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add device_type property for the pcie devicetree nodes
in sun.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I8b1591ea83784ffc19c928e1af73117657ac7f15
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add initial devicetree nodes and entries to support
PCIe RC0 port configuration on sun.
Change-Id: I3b7419bfd376a51388785cc4e2f9702ddaabe397
Signed-off-by: Lazarus Motha <quic_lmotha@quicinc.com>
