Change the pcie devicetree node names to be in line with the
pci-bus.yaml format.
Change-Id: Ic7d5158f988163e6053df27aa8084a1a1f5b8f0d
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add device_type property for the pcie devicetree nodes
in pineapple.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I212e023880ed8373eb17379754da84b6947d1171
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Correct the following pcie1 dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I048275f388f31fe71b157f1f9ab4aaf5eec6131b
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Correct the following pcie dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
qcom,pcie-clkreq-gpio -> qcom,pcie-clkreq-pin.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I79454ef04a69d5427e32c45042304809cdcb886c
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
