Add new "qcom,adc5-gen4" property to flag ADC5 GEN4 channels.
Change-Id: I271b6e74d36721f6c38bd1f3d68e47bc5393b04d
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Remove the qcom,cesta-l1sub-timeout-ext-int property as its no
longer required due to recent changes in the pcie driver using the
change commit b53d4aa20ee7 ("pci: msm: Add support to enable
PCIE CESTA clkreq config").
Initially this property was intended to be used to enable the BIT(3):
PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA
is enabled and the platform is not pineapple.
Currently the pcie driver will by default set this BIT(3) when CESTA is
enabled and the qcom,pcie-clkreq-offset property is present. Since the
qcom,pcie-clkreq-offset property will not be present when CESTA
is enabled on pineapple, pcie driver will not touch the
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register.
Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when
qcom,pcie-clkreq-offset property is present and CESTA is not present
which is the case of pineapple platform when CESTA is enabled. And
this case is also taken care of by the pcie driver without the need
for qcom,pcie-clkreq-offset property.
Below are the required cases that needs to be taken care of by the
pcie driver.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | BIT(0) set | BIT(3) set | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | need to set| need to set| non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | set by | Not | pineapple |
| | default | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | need to | Not | pineapple |
| | unset | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset
property in the following way.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | qcom,pcie-clkreq-offset | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | YES | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | NO | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | YES | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This reverts commit 704e2e0186.
Reason for revert: No longer needed once 1ns frequency is disabled.
Change-Id: I2355fff08acf5746efdce7562df99f83bba4696b
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
PMK8550 has a couple of high resolution PWM channels which can support
from 8-bit to 15-bit PWM. Add it.
Change-Id: I277bca101546de07ffc8bb34380fc8bbdea10a92
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Updating build files with ATP platform DT support on Sun SoC.
Change-Id: I6e0d614d5ea3c6d781c432e8e5dde900aa1aa02f
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
The qcom,display heap is used for camera usecases.
Change-Id: Ib937670c33284fb2dc624258fd8e5978b4405ace
Signed-off-by: Vijay Kumar Tumati <vtumati@quicinc.com>
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
After hotplugging in memory, automatically online it to the movable zone.
Change-Id: I1dde15451e78196fc261c0bd9b25cdfa91749c4c
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add DT support for RCM platform on Sun SoC.
Change-Id: I1dc5b3b432b2126b0a380437a2a19854aa1db5f1
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Correct the SID ranges for the cam_hf qtb and the mdp_hf
qtbs.
Change-Id: I0d6127248bbfac122d14ca2c600dd81d3a7d5550
Signed-off-by: Oreoluwa Babatunde <quic_obabatun@quicinc.com>
Add qcom,sensitive property in vm-config node for Sun VM.
Change-Id: I5b2781df510f59d7c3f779eecb55c7bc64fad84c
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add devicetree soccp node for Sun SoC. In addition to existing smp2p INT's
SOCCP H/W needs 2 more INT for controlling the power state of the H/W.
sleep bit and wakeup bit on master kernel corresponds to these INT.
Change-Id: I00d2f6a3fb76f306fa070df87f22bb2d07cb4c3b
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Add DT support for ATP variant on Sun SoC.
Change-Id: Icb07c87ca0ed07c81e0d3bf42e5c69147d6f1807
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add compatible string for ATP variant on Sun SoC.
Change-Id: Ibaa26b372af475afe291c78c57a1e32d4a76ea93
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add snapshot of devicetree bindings from commit (bb95f5ff94:
"ARM: dts: msm: Add probe dependency to PMIC PON Log driver")
for qcedev. Update the bindings from .txt to .yaml.
Change-Id: I7e46035c6ac66c14e932c009d4a1291ec6127001
Signed-off-by: Daniel Perez-Zoghbi <quic_dperezzo@quicinc.com>
Use 0x17 pmu event as miss-ev in llcc memlat for sun.
Change-Id: Ifbd710d9fcb24f7442f2b6d6d8e94f858e48c326
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Enable low power modes for sun through kernel command
line parameters.
Change-Id: Ifd4b8fcce8d6b2c0b4f6a4c2dcb088ae8c8fa661
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
