This change adds pentile pack type for SPR panel.
Also corrected the pack type to "BG-RG Type B" for sun target.
Change-Id: I385a554b062b6d1fa86ff1ced8ead4fe791bcdd5
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
This change adds battery_charger support for qrd/mtp
and qupv3_se15_i2c support for cdp on sun target.
Change-Id: I0fd532d386e8aff9212410e80e7183beeae7af3b
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Change adds HDR capability for panels on sun target
Change-Id: I2e4dc6e037c3dc465103ee9c1c4465be7173c841
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
Driver needs to set esync clock's parent under a gating condition,
which is not available at the point where the clocks under MDSS DSI
node are parsed. Moves the esync RCG clock to SDE DSI instead.
Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Update sde-qos-cpu-mask value for sun target.
Change-Id: I1e3a94b276d7ac31d693bdc73a46cc40189d5c43
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Update in height alignments from 40 to 20 for FHD 60FPS cmd mode to
match DSC slice settings. The values should be integral multiple of
height defined for panel.
Change-Id: I41e2e5b3ec0b75a6eb2f39879356c92239853f74
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Add the sde_rscc register offset to help in accessing the cesta
status registers.
Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds the identification of rc_override_v1 and remove
24/20Hz for wqhd command dphy mode due to panel limitation.
Change-Id: I6ec180fa5ffe25ca914ecd270bbe55c3a64e14d8
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Adds pinctrl configuration to pass esync signal through from hw block
to output pin. Also adds esync and oscillator clocks, and makes the
DSI PLL clock available to parse for setting clock parent.
Change-Id: I09ac2d1a334546452176285712d8c953f94aecf2
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Adds variant of CSOT panel with AP SPR in video mode.
Change-Id: I01035e333822b37c4ebc5ab4cd1d728d0638e979
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
This change adds pentile pack type for SPR on sun target.
Change-Id: I9d1da6be1262d806e1e8f1820fd3b844d40cfbf3
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
This change add scaling up code in on command for FHD+ csot panel.
Change-Id: Idb98ba4080b7030c317b6530a06912baf432fc79
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Update height alignments from 20 to 40 for HD 60FPS cmd mode to
match DSC slice settings. The roi height and width alignment
must be integral multiple of DSC slice height and width.
Change-Id: I127af4c4e6a453757f60677bac787cd4bd4b6d07
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Add secondary display support on NT37801 panel for Sun QRD and
MTP target.
Change-Id: I2c8579f4343ae15109942e545e2f76e55aadf038
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Update unsecure context bank to exclude memory region allocated to
display splash, ramdump and demura.
Change-Id: I9a3d00c3943b2a5c94914856f498cb62a7fc4dfa
Signed-off-by: Jayasri Sampath Kumaran <quic_jsampath@quicinc.com>
This change add a mode with FHD+ resolution for csot panel.
Change-Id: I72c5efc4159fb0ed99fcaa5fd93069601993d598
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
This reverts commit 33797c66a4.
Reason for revert: retention to be handled through clock api.
Change-Id: Ib7e54924779e78f839a80e91342344c28b877b0c
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Move the MDSS GDSC from regulator to power-domain on
sun target. This will align with upstream usage.
Change-Id: I8e5e3330fa0d13d496336f82d3eaee44c921f903
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add additional device trees and msm-IDs to support an additional
package ID. Also update board id for QMP1000 V6 variant on MTP for
sun target.
Change-Id: Ic6287bc0052cb44321674e16c74631c8a75f2aef
Signed-off-by: Jayasri Sampath Kumaran <quic_jsampath@quicinc.com>
Add display cesta related DT node and configs on sun target.
Move the GDSC & MDP core clk from mdp to cesta node, as it will
be controlled through cesta. Add the cesta related register
offsets in trusted-vm DT for incoming io validation during the
transition.
Change-Id: I1f5ebf59db2169dfae3801f572c80af9e016e667
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
