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Merge "ARM: dts: msm: add esync pinctrl and clocks"

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qctecmdr
2024-06-04 18:09:31 -07:00
committed by Gerrit - the friendly Code Review server
parent a65088bd55 bdedd83bd9
commit 44357ae6f6
3 changed files with 74 additions and 8 deletions
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14
display/sun-sde-display-common.dtsi
View File

@@ -130,9 +130,10 @@
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
pinctrl-names = "panel_active", "panel_active_with_esync", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend>;
pinctrl-1 = <&sde_dsi_active &sde_te_active &sde_esync0_active>;
pinctrl-2 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend>;
qcom,platform-te-gpio = <&tlmm 86 0>;
qcom,panel-te-source = <0>;
@@ -149,9 +150,10 @@
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
pinctrl-names = "panel_active", "panel_active_with_esync", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active &sde_esync1_suspend>;
pinctrl-1 = <&sde_dsi1_active &sde_te1_active &sde_esync1_active>;
pinctrl-2 = <&sde_dsi1_suspend &sde_te1_suspend &sde_esync1_suspend>;
qcom,platform-te-gpio = <&tlmm 87 0>;
qcom,panel-te-source = <1>;

54
display/sun-sde-display-pinctrl.dtsi
View File

@@ -111,4 +111,58 @@
};
};
};
pmx_sde_esync: pmx_sde_esync {
sde_esync0_active: sde_esync0_active {
mux {
pins = "gpio88";
function = "mdp_esync0_out";
};
config {
pins = "gpio88";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_esync0_suspend: sde_esync0_suspend {
mux {
pins = "gpio88";
function = "mdp_esync0_out";
};
config {
pins = "gpio88";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_esync1_active: sde_esync1_active {
mux {
pins = "gpio100";
function = "mdp_esync1_out";
};
config {
pins = "gpio100";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_esync1_suspend: sde_esync1_suspend {
mux {
pins = "gpio100";
function = "mdp_esync1_out";
};
config {
pins = "gpio100";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
};
};

14
display/sun-sde.dtsi
View File

@@ -312,10 +312,15 @@
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&mdss_dsi_phy0 1>,
<&dispcc DISP_CC_ESYNC0_CLK>,
<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
};
&mdss_dsi1 {
@@ -326,10 +331,15 @@
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&mdss_dsi_phy1 1>,
<&dispcc DISP_CC_ESYNC1_CLK>,
<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
};
&mdss_dsi_phy0 {