Set default Q2SPI clock to 32MHz by using
dt property "q2spi-max-frequency".
Change-Id: I174876a08da50851f538a4cf5fd337e7c21ce76e
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Add power domain for NCC related QDSS components on sun.
Change-Id: I5396c6fc4a19e2ec09e4ecee66b9a06502ad2051
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Add multiple output port support for funnel-gfx_dl funnel on sun.
Change-Id: Ie61c07b80efde4d1e445283cc393fd2509095cfb
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Enforcing access restrictions for eSE secure GPIO
by tagging it as reserved.
Change-Id: Ia525cafe06689708d323ddbc6b65f9ddc4b4647a
Signed-off-by: PRANAY BHARGAV BHAVARAJU <quic_pbhavara@quicinc.com>
3.5mm MTP platform needs to support v8 power grid instead of
v6 power grid.
Change-Id: I60e6396bba3fc17f4ed7e28504f673dad9b706ba
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Change vdd io current level of sdhc_2 to set 22 mA load to follow
up new Power Grid on SDC2 vdd-io pads regulator lpk. The previous
5.6 mA is not able to reflect real drawing current. It may cause
OCP issue as 5.6 mA voting load from SW is not enough to let SDC2
vdd-io regulator work on HPM, but the real drawing current may
exceed LPM OCP threshold.
Change-Id: I3eef0d1269d424341fea5493b467af26c5f203fa
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
Although this is already present in CONFIG_CMDLINE in gki_defconfig, it
appears to be being overridden by the commandline specified in devicetree.
Change-Id: If61b4cfd11a15a7c36fb01875b7c77ac7c5bde8b
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Setting dma32_disable causes all memory to be placed in ZONE_NORMAL,
and reduces overhead in page allocation.
Change-Id: I770fe2688081b457a121afd23d6d924423680e5f
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add 4.5 MB for use by minidump_memory driver.
Add 2 MB for use by memshare IMS usecase.
Change-Id: I5f3897e24dd4b7a1c7bd3f883c4837eaa3ca384a
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Fix the interrupt line for wdog INT to EDGE triggered.
Change-Id: Id9ca3f3a632b95bfa17cedacda0936845413ded1
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
qcom,ramoops driver takes memory dynamically
available from a given range and give it to
ramoops for its usage.
Change-Id: I94ece0f9d25719e240ecb5c7f47a3b1fe83fbab1
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Loadable section memory of FingerPrint(FP) Sensor TA
has to be increased which requires increase in qseecom_ta mem.
Change-Id: Ie0a31662cd7b05f3aff0a41c275089ed7684d8b0
Signed-off-by: Akhil Budampati <quic_abudampa@quicinc.com>
Add the list of PCIe SM registers that need to be dumped
to the PCIe dt node in sun.
Change-Id: Ic2e0518ac611ef5e409f88dcd0f69eb2ce4d8566
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Removed SP PBL Patch Version Register from sun dtsi
since it is no longer used.
Change-Id: I52b28ed1a07676188a39c09b72c0e2364cfc0ac2
Signed-off-by: Magesh M <quic_murugan@quicinc.com>
Based on the DisplayPort CTS PHY test, current EQ settings were not
sufficient to pass the test margins. Adjust the EQ from 2dB to 0dB as
recommended by the display team based on the results.
Change-Id: Ib0b6c7f9ccb2d8385d57be0aceda704dc98f7f18
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Add device nodes to configure PDP mailbox and add support
for PDP logging on both PDP cores.
Change-Id: I2393334d33373df3447f5140cc66cd7624faf0cd
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Currently ibi gpii irq configured wrongly, due to this
ibi controller doesn't generates irq. To solve this
rectified the gpii irq number.
Change-Id: I05c7f41463c19ffbf095c2ec6d217210f8d2aa8f
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
For AON usecase switching from HLOS to SSC needs TLMM function to be
non IBI, hence during sleep mode change function of the TLMM to QUP
mode so that SSC can work with IBI disable without any issue.
Also ensures to restore back the TLMM Function to IBI mode when HLOS
i3c usecase starts.
Change-Id: Id6a5cdeafe2c3ee50186c0020831e4eb8f329f95
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Currently, charger FW configures and enables ship mode in parallel with
shutdown activity. This can cause a race condition leaving the device in
a bad state if the device is powering off while SW is still issuing SPMI
writes.
Add the battery charger "qcom,ship-mode-immediate" property on Sun
platforms so that ship mode will be configured immediately by charger FW
after user sets ship_mode_en.
Change-Id: I55a78c7b5c59b8b82519713fb4267d081c54a92f
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add the pm8550_pa_therm2 ADC channel as well as the corresponding
thermal zone device which can be used by thermal SW.
Change-Id: I2c583ca8c00a67a122b6c1b7622436bcf8058165
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Mark GCC clock node as GenPD provider and disable the
PCIE GDSC regulator nodes.
Change-Id: I98fc6709592c393259da77443d4b6e580e61a0b8
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Mark dispcc clock node as GenPD provider and disable the
display GDSC regulator nodes.
Change-Id: I91cf788254ca0bd78a02dc4b196745da380fb74b
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
