According to the Hardware Programming Guide, when going into hibern8,
select XO clock (RPMH_CXO_CLK) clock as the parent of the phy symbol
mux clocks (GCC_UFS_PHY_RX/TX_SYMBOL_0/1_CLK_SRC). When exiting the
hibern8, select the phy symbol clocks (UFS_PHY_RX/TX_SYMBOL_0/1_CLK)
as the parent of the phy symbol mux clocks.
Change-Id: I624f98c39b7548dc2a9a5207d82600bb69ac41d5
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add dispcc_mx clock controller node as a child node of dispcc
node to register dispcc mx clocks on sun platform.
Change-Id: I1ade67a4f2c09135800b3d5603c8e18a86450de7
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Use alias to reduce dev mistake of not using
proper path for serial console.
Change-Id: Ie588cc39b8f9e167b323abb9901114b547c278fc
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Commit I4a4ae323ea0 ("kernel-scripts: sun: Update not_preferred
settings") has updated the default isolated CPUs for Gold
clusters.
Since Isolation CPUs is preferred CPU for irq handling and not prefered
for task handling, update the ESI affinity for CQ to address the same.
Change-Id: I6fbb274d52418e9ebb965c6414c449543796d734
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Currently cpufreq delayed work is queued with delayed
timer as 30ms. On expiry, we monitor load and then
enable storage boost feature if load exceeds certain
predefined threshold.
Unlike pineapple, we are monitoring the load request only
on prime/large cluster and not on medium cluster.
This is causing some additional delay to reach the
threshold required to enable storage boost feature.
Benchmark tools like Antutu completes read or write IO
within 120-130ms which mean any small delay can impact
Antutu to large extent. Hence add medium clusters to perf
score similar to pineapple so that load on medium cluster
along with large cluster is considered.
This will decrease the window time to reach the threshold
to start the storage boost and hence improve Storage
benchmark performance.
Change-Id: I8563cffc4da8fa7729d38fc71c8996b20b79b1ec
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
(cherry picked from commit 167166ab42)
Add support for LowSVS on ICC for soccp.
Change-Id: Ic845482060c91edf4e9bab3f2248dd6299f43194
Signed-off-by: Auditya Bhattaram <quic_audityab@quicinc.com>
Currently cpufreq delayed work is queued with delayed
timer as 30ms. On expiry, we monitor load and then
enable storage boost feature if load exceeds certain
predefined threshold.
Unlike pineapple, we are monitoring the load request only
on prime/large cluster and not on medium cluster.
This is causing some additional delay to reach the
threshold required to enable storage boost feature.
Benchmark tools like Antutu completes read or write IO
within 120-130ms which mean any small delay can impact
Antutu to large extent. Hence add medium clusters to perf
score similar to pineapple so that load on medium cluster
along with large cluster is considered.
This will decrease the window time to reach the threshold
to start the storage boost and hence improve Storage
benchmark performance.
Change-Id: I8563cffc4da8fa7729d38fc71c8996b20b79b1ec
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Disable slub debug option through command line for sun.
Change-Id: Ide22d13c6a39e9a6ade53435c3e1072efd493206
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
This change will update dll_usr_ctl to the recommended value.
Change-Id: I345b59546faf950645c0f173ac145e40124170f1
Signed-off-by: Sachin Gupta <quic_sachgupt@quicinc.com>
APPS needs to place proxy votes to ddr and cnoc when the SOCCP is in D0.
Change-Id: Idfa93910b51c6df033ea010480c1a8adeacd4af5
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
SOCCP_SOCCP_SPARE_REG0 is used to check D0 status of SOCCP.
TCSR_SOCCP_SLEEP_STATUS is used to check D3 status of SOCCP.
Change-Id: Icee37cddb0b7ef303962cab0d9a8f37a211a05da
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
SW drv3 may be used sometimes by display panel. Add it.
Change-Id: I03fc0bee08c44447caf689b747b054f4aa62ffca
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
This feature is not supported on sun, and its memory region is now
reused by hypervisor for other purposes.
Change-Id: I027335e4f8358bed7cb692120ca0ba0b601b472e
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Remove unused SW DRVs as keeping them makes them register
with IRQs and leading to spurious IRQs.
Change-Id: Iba8723b7ac734286668158fe793bde97f3f31eda
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
legacy SoCs had shutdown ack only available to modem DSP
since waipio, it is even available for ADSP and CDSP and since
we are adding shutdown ack timeout which would wait for these
ack interrupts. Let's add them for ADSP and CDSP as well.
Change-Id: I75c427be29d8d762617ccc1e595929edb9ff2c3b
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Add CPUCP fast device tree entry to get mailbox channel id and cpus to
be controlled with fast.
Change-Id: Ibfc2db806adf97985bf3921fac1244032749d61a
Signed-off-by: Lingutla Chandrasekhar <quic_lingutla@quicinc.com>
Remove the hard coded class cpus and replace them with their
phandles.
Change-Id: I283ac79d64d945e12477f61a67b058574bde7031
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
There is 512K of DDR in a section memory and the rest is carveout in a
memory region [0x98000000 a0000000). As section size is 128M, which
require 2M of memmap. Lose this 512K to save (2M - 512K) of memory.
CRs-Fixed: 3792207
Change-Id: I5fa1f7a366eefd464e67099ff1835dc84423d18b
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Update llcc gold bwmon to have its memory mapped as
non-early for sun.
Change-Id: I190283c136736b069eaed6805f5813ceb0c2d38f
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
