Commit Graph

2023 Commits

Author SHA1 Message Date
Vishnu Santhosh
04904d20a8 ARM: dts: msm: Add smem nodes for sdxkova
Add smem nodes for sdxkova SoC.

Change-Id: I489aa0d9341cc48350a37c244135909d1686b0b5
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
2024-09-06 12:10:36 +05:30
Sayan Dey
160a80d44a ARM: dts: msm: Add LLCC node for sdxkova SoC
Add LLCC node for sdxkova to enable last level cache controller.

Change-Id: Ief1651c1bb72a4c8f170b2fc40e9879ab4781b3d
Signed-off-by: Sayan Dey <quic_sayand@quicinc.com>
2024-09-05 11:28:18 +05:30
QCTECMDR Service
cc13f7536b Merge "ARM: dts: msm: Add CPUSYS_VM support for Tuna" 2024-09-04 04:13:41 -07:00
QCTECMDR Service
c03efb9a8d Merge "ARM: dts: qcom: Include IPCC test node for sdxkova" 2024-09-04 00:28:10 -07:00
QCTECMDR Service
9eec6eeeea Merge "ARM: dts: msm: add mmc wrapped key support to ravelin" 2024-09-03 19:13:27 -07:00
QCTECMDR Service
03e09aa933 Merge "ARM: dts: qcom: sdxkova: update interconnect providers with bcm-voter-names" 2024-09-02 11:04:36 -07:00
QCTECMDR Service
e640fe35c1 Merge "ARM: dts: msm: Spilt memdump entries to static and dynamic" 2024-09-02 11:04:36 -07:00
Keval Kulkarni
c26f69e0e0 ARM: dts: qcom: Include IPCC test node for sdxkova
Include IPCC test node for sdxkova, so IPCC kernel-tests can
run on sdxkova.

Change-Id: I96e4f925d62eec54455b8f03f46217fc402e43a5
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-02 15:20:15 +05:30
Keval Kulkarni
2e93118b13 ARM: dts: msm: Add ipcc node for sdxkova
Add ipcc node for sdxkova to enable inter processor
communication controller.

Adjust reg format for tz-log node.

Change-Id: I5519f5b8bfc02b2c85c1654a2f39c4ec61fdee9f
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-02 15:18:12 +05:30
QCTECMDR Service
821bb54eb2 Merge "ARM: dts: msm: Enable SMMU in kera" 2024-09-02 02:27:37 -07:00
Hrishabh Rajput
262363b430 ARM: dts: msm: Add CPUSYS_VM support for Tuna
Add reserved memory node for CPUSYS_VM and add support for CPUSYS_VM
loading for Tuna target.

Change-Id: If797d5038601ce17208e4da511edbe77c1ad2c9a
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
2024-09-02 12:27:19 +05:30
QCTECMDR Service
17b320bdf1 Merge "ARM: dts: msm: add SD/eMMC regulator devices for sdxkova" 2024-09-01 21:48:44 -07:00
QCTECMDR Service
1257dafcf8 Merge "ARM: dts: msm: Enable SMMU S1 translations for USB on sdxkova" 2024-09-01 21:48:44 -07:00
Raviteja Laggyshetty
481c435dd1 ARM: dts: qcom: sdxkova: update interconnect providers with bcm-voter-names
Update interconnect provider device nodes with bcm-voter-names to route
the bandwidth requests through appropriate DRV.
Add necessary clock handles to access the QoS registers.

Change-Id: I5c271682e0b3f094d85fa759e19f8a89ae8f0eff
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2024-09-01 21:42:05 -07:00
QCTECMDR Service
ebdec40ada Merge "ARM: dts: qcom: Add clock controller nodes support for sdxkova" 2024-09-01 16:58:34 -07:00
QCTECMDR Service
d1c3025fcd Merge "dt-bindings: clock: Add debugcc bindings for SDX75" 2024-09-01 08:25:10 -07:00
QCTECMDR Service
76347faf0d Merge "ARM: dts: msm: Add evacc support for sun v2" 2024-09-01 08:25:09 -07:00
Shashikala Katthi
7b95da86d1 ARM: dts: msm: add mmc wrapped key support to ravelin
Add support for ice wrapped keys to the MMC DTSI entry
on ravelin.

Change-Id: I96af5ceddf4522f97bbefcc3289c843e828ef580
Signed-off-by: Shashikala Katthi <quic_skatthi@quicinc.com>
2024-08-30 18:40:50 +05:30
Jishnu Prakash
f024728173 ARM: dts: msm: add SD/eMMC regulator devices for sdxkova
Add regulator device for the external gpio-controlled regulator
which powers the SD Card and eMMC on sdxkova boards.

Change-Id: I0b07342dda4d07e51ebcd63a2ca52f7a77ddc590
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
2024-08-29 22:20:27 -07:00
Prashanth K
e229a174cd ARM: dts: msm: Enable SMMU S1 translations for USB on sdxkova
Enable SMMU S1 translations for USB on sdxkova.

Change-Id: I6ce61af54bb0a186eb35498160f49fb4f399f51a
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
2024-08-29 22:08:59 -07:00
Prashanth K
35b268fa14 ARM: dts: msm: Add USB3 SSPHY DT nodes for sdxkova
Add QMP USB3 SSPHY device-tree nodes for sdxkova.

Change-Id: I7157198092c703b1c8e9e6b40f984959bfaab89e
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
2024-08-29 22:08:46 -07:00
Prashanth K
a42a681f5d ARM: dts: msm: Add USB DT nodes for sdxkova
Add DWC3 USB controller device-tree nodes for sdxkova.

Change-Id: I9a44ad5d49dfb8bdadca04696c8580e283b5f2ec
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
2024-08-29 22:08:14 -07:00
Imran Shaik
c87edbce6a ARM: dts: qcom: Add clock controller nodes support for sdxkova
Add support for GCC, DEBUGCC, GDSC and CPUFREQ-HW-DEBUG nodes
for sdxkova platform. While at it, update the cpufreq default
governor to performance.

Change-Id: Icba0ba93cf82e576e7b645c247d2d0e7f0f6da3f
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
2024-08-30 08:01:02 +05:30
Kamal Wadhwa
a352445062 ARM: dts: msm: Add regulator support for sdxkova
Add regulator support for sdxkova.

Change-Id: I0d81c87c1d05144f8c9fe72ee3bf822541f36e61
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
2024-08-30 07:58:55 +05:30
QCTECMDR Service
7ed138f492 Merge "ARM: dts: msm: Add smmu ACLTR values for tuna" 2024-08-29 10:24:30 -07:00
QCTECMDR Service
919409d41a Merge "ARM: dts: msm: Add thermal zones and ADC channels for tuna" 2024-08-29 10:24:30 -07:00
Uttkarsh Aggarwal
540f17c507 ARM: dts: msm: Enable SMMU in kera
Enable SMMU for the USB controller on kera.

Note: Currently in bypass mode.
Change-Id: I59245b14cf20ddbfdc4782f4f23f6d702817a03c
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
2024-08-29 14:02:06 +05:30
QCTECMDR Service
2a016c0385 Merge "ARM: dts: msm: Add boot_device_type for Ravelin" 2024-08-29 01:25:41 -07:00
QCTECMDR Service
4a37cecca8 Merge "ARM: dts: msm: Add secure-buffer device for tuna" 2024-08-29 01:25:41 -07:00
QCTECMDR Service
35bfef85fa Merge "ARM: dts: msm: Disable pressure control group feature for Parrot" 2024-08-29 01:25:41 -07:00
QCTECMDR Service
11c93de9c3 Merge "dt-bindings: Add bindings for sdxkova llcc" 2024-08-29 01:25:41 -07:00
QCTECMDR Service
50aeed3199 Merge "ARM: dts: msm: Add clock and regulator for kgsl-smmu for tuna" 2024-08-29 01:25:41 -07:00
Imran Shaik
fc88476b6b dt-bindings: clock: Add debugcc bindings for SDX75
Add DEBUGCC bindings for SDX75 Platform.

Change-Id: Ibb1636f26b04009198c6045080f981e93e07a36c
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
2024-08-29 11:04:47 +05:30
Kavya Nunna
3eb6601fe5 ARM: dts: msm: Add thermal zones and ADC channels for tuna
Add thermal zones and ADC channels for tuna for pmk8550,
pm8550ve, pm8550vs and pmxr2230.

Change-Id: Ic95d475bdf9488fc46444908283e1bbe4a314012
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
2024-08-28 22:18:32 -07:00
Kavya Nunna
d67eea973f ARM: dts: msm: Add volume-up key support for tuna
Add changes to support volume-up key for tuna.

Change-Id: I37770a4368220b95a3458a75a3a58d9f604dc0bc
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
2024-08-28 22:17:15 -07:00
QCTECMDR Service
47f56ac1da Merge "ARM: dts: msm: Add rsc device node for sdxkova" 2024-08-28 11:54:24 -07:00
QCTECMDR Service
440c8e972a Merge "ARM: dts: msm: Enable rmtfs module for tuna" 2024-08-28 11:54:24 -07:00
Kishor Krishna Bhat
9cc2ae780b ARM: dts: msm: Add boot_device_type for Ravelin
Add boot_device_type support and flag non-removable
for ufs node to check if the boot device is emmc or ufs.
Remove qcom,ufs-dev-revert to identify ufs device Version.

Change-Id: If57051a722970567cd89ad19c7aa0eb0bb555d64
Signed-off-by: Kishor Krishna Bhat <quic_kishkris@quicinc.com>
2024-08-28 08:57:05 -07:00
Sachin Gupta
aba1abe100 ARM: dts: msm: Enable rmtfs module for tuna
Add rmtfs properties to enable remote storage access module.

Change-Id: I23188199f91399895c95efe02d85905a7e66d185
Signed-off-by: Sachin Gupta <quic_sachgupt@quicinc.com>
2024-08-28 03:06:02 -07:00
QCTECMDR Service
a50aff28a4 Merge "ARM: dts: msm: Add QUPv3 UART console node for kera" 2024-08-28 02:48:47 -07:00
QCTECMDR Service
dcff40e63b Merge "ARM: dts: qcom: Add support for m2 board on sdxkova SoC" 2024-08-28 02:48:47 -07:00
Raghavendra Kakarla
d1656ed916 ARM: dts: msm: Add rsc device node for sdxkova
This change adds the apps rsc device node.

Change-Id: Ia2fb73f6fce7088884d88f71fee5486b997d63dd
Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com>
2024-08-28 14:31:23 +05:30
Sayan Dey
069e332799 dt-bindings: Add bindings for sdxkova llcc
Add bindings for sdxkova llcc node.

Change-Id: I4840d434f9dd50ccb47de078cd44ba2261e5ade2
Signed-off-by: Sayan Dey <quic_sayand@quicinc.com>
2024-08-28 12:37:29 +05:30
QCTECMDR Service
7630a544bc Merge "dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0108 and PM7550BA bindings" 2024-08-27 10:51:35 -07:00
QCTECMDR Service
fbea4f41a4 Merge "ARM: dts: msm: Modify SMMU reg field format for sdxkova" 2024-08-27 10:51:35 -07:00
QCTECMDR Service
87aa233c36 Merge "ARM: dts: msm: Add UI peripherals support for tuna" 2024-08-27 10:51:35 -07:00
Swetha Chikkaboraiah
03d3d65753 ARM: dts: msm: Disable pressure control group feature for Parrot
Disabling pressure control group feature for Parrot SOC.

Change-Id: I42237e66c3a34893d768ded5f6ce7511f78cdfa0
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
2024-08-27 05:27:52 -07:00
Khaja Hussain Shaik Khaji
bc5963cb3b ARM: dts: qcom: Add support for m2 board on sdxkova SoC
Add the m2 board support on sdxkova SoC.

Change-Id: If690aaa6374972732df1916738b58651598253ff
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-08-27 16:49:56 +05:30
Kavya Nunna
4b440df8a7 dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0108 and PM7550BA bindings
Update the Qualcomm Technologies, INC. PMIC GPIO binding documentation
to include compatible strings for PMIV0108 and PM7550BA PMICS.

Change-Id: I05280b84374c4f74e43e2205844ad80aff40a33f
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
2024-08-26 23:56:13 -07:00
Bibek Kumar Patro
3c46ebee9d ARM: dts: msm: Modify SMMU reg field format for sdxkova
Modify SMMU register field format as per the parent SoC
address and size cells.

Change-Id: Ifce3e103601a82b1b9f6295d6abef826f917b0fc
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
2024-08-26 23:14:57 -07:00