Add board id for Sun MTP with 3.5mm Kiwi WLAN V8 Power Grid.
Change-Id: I9bd6275a37275e4f10f8c4efe3bf7bf95f581776
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This patch adds APQ support for ATP platform.
Change-Id: I6b91f7151cc88834782fc6068d3adfc2f2024b84
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Enable 4ppc mode for DP on sun platform to support higher resolution
mode.
Change-Id: I54208fd665710b5162bf20b1f676ed59c585226b
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Increased clock rate with 2% config for 10 bits dphy cmd panel
due to transfer time go beyond cause frame-drop with cesta enabled.
Change-Id: I30fed53879bcf04ade37ff737b27c87f82740c67
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Sync state will remove the disp_cc device vote once the device
driver probe is complete. It removes the DSI clock vote early
for continuous splash usecase because DSI driver takes its vote
in component binding instead of device driver probe.
It is better to keep disp_cc vote for components till respective
device probe complete and they register themselves to master
component. This change adds disp_cc vote for smmu_sde_unsec,
smmu_sde_sec, sde_wb1 and sde_wb2 devices to retain vote till
bind_all API is called.
Change-Id: Ie6e39cb53c4fdd93a1ce7d07a0fc99a250235902
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Change adds HDR capability for panels on sun target
Change-Id: Ibb106a5651579535a4ede964dc10fcd8b086a562
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
Driver needs to set esync clock's parent under a gating condition,
which is not available at the point where the clocks under MDSS DSI
node are parsed. Moves the esync RCG clock to SDE DSI instead.
Change-Id: I0a94ecdf0dc3318baa0685eb78b14dbc9e052538
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Update sde-qos-cpu-mask value for sun target.
Change-Id: I9eeb298857d739bdf19620a9dde2c064dceea1ae
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Change adds HDR capability for panels on sun target
Change-Id: I2e4dc6e037c3dc465103ee9c1c4465be7173c841
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
(cherry picked from commit 6d718caa81)
Driver needs to set esync clock's parent under a gating condition,
which is not available at the point where the clocks under MDSS DSI
node are parsed. Moves the esync RCG clock to SDE DSI instead.
Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Update sde-qos-cpu-mask value for sun target.
Change-Id: I1e3a94b276d7ac31d693bdc73a46cc40189d5c43
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
This change adds pentile pack type for SPR panel.
Also corrected the pack type to "BG-RG Type B" for sun target.
Change-Id: I385a554b062b6d1fa86ff1ced8ead4fe791bcdd5
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
This change adds battery_charger support for qrd/mtp
and qupv3_se15_i2c support for cdp on sun target.
Change-Id: I0fd532d386e8aff9212410e80e7183beeae7af3b
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Change adds HDR capability for panels on sun target
Change-Id: I2e4dc6e037c3dc465103ee9c1c4465be7173c841
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
Driver needs to set esync clock's parent under a gating condition,
which is not available at the point where the clocks under MDSS DSI
node are parsed. Moves the esync RCG clock to SDE DSI instead.
Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Update sde-qos-cpu-mask value for sun target.
Change-Id: I1e3a94b276d7ac31d693bdc73a46cc40189d5c43
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add the sde_rscc register offset to help in accessing the cesta
status registers.
Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Adds VHM related device tree properties to bindings and documents
their meaning and usage.
Change-Id: Idc43ba7bcfe1c8d9960aa00b3d807b74789d57f0
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Update in height alignments from 40 to 20 for FHD 60FPS cmd mode to
match DSC slice settings. The values should be integral multiple of
height defined for panel.
Change-Id: I41e2e5b3ec0b75a6eb2f39879356c92239853f74
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Add the sde_rscc register offset to help in accessing the cesta
status registers.
Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
