Commit Graph

13 Commits

Author SHA1 Message Date
Swetha Chikkaboraiah
9c878c4021 ARM: dts: qcom: Update qup_iommu_region node name
Currently single qup_iommu_region is getting created,
leading to DMA RX inactivate.
So update node name for qup_iommu_region0 and qup_iommu_region1.

Change-Id: Id1355c98a07f912e6275ac3c2fb7504ae9f22f53
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
2024-12-12 10:10:20 +05:30
Prakash Yadachi
ba19503906 ARM: dts: msm: Add memory and clock support for ravelin-VM
Add memory and clock support for qup for ravelin-VM target.

Change-Id: I8b9fb0a2e1f3be9864ddd074aec5d97d9eda4527
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-11-19 14:47:13 +05:30
Swetha Chikkaboraiah
f5dc7ce0a9 ARM: dts: msm: Update qup_iommu_region
Update node qup_iommu_region for parrot and ravelin.

Change-Id: I488e3eb0a1577b7e1aafbdfd91efd6e12fdfd55b
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
2024-11-05 21:10:42 -08:00
QCTECMDR Service
3abb707021 Merge "ARM: dts: msm: Ignore dependencies on children by PM framework" 2024-09-27 03:23:38 -07:00
Prakash Yadachi
79824b3a5b ARM: dts: msm: Ignore dependencies on children by PM framework
Change https://lore.kernel.org/all/20230525113034.46880-1-tony@atomide.com
registers serial core controller as a child of msm uart device.

Since child should suspend first, due to the child's auto suspend
delay (SERIAL_PORT_AUTOSUSPEND_DELAY_MS), additional 500msecs
delay is added during msm_geni_serial_runtime_suspend.

Added new dtsi flag 'qcom,suspend-ignore-children', to ignore
dependencies on children by runtime PM framework, this helps to
exit quickly from msm_geni_serial_runtime_suspend and save power.

Change-Id: I4b552c76a8b25fcad92762eba036ffe1797c4e26
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-09-24 14:31:50 +05:30
Prakash Yadachi
6b30cd02c5 ARM: dts: msm: Add interconnect changes
Add gem_noc and config_noc interconnect
changes for Parrot and ravelin target.

Change-Id: Ia94f8503d7a580fefb3a68efac1a24d525083294
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-09-04 23:18:21 -07:00
QCTECMDR Service
71d1b7a014 Merge "ARM: dts: qcom: Update proper clock name" 2024-07-17 10:36:53 -07:00
QCTECMDR Service
51e42b52f3 Merge "ARM: dts: msm: Add interconnect-names for Ravelin" 2024-07-16 21:19:06 -07:00
Prakash Yadachi
e0529a17d7 ARM: dts: msm: Add interconnect-names for Ravelin
Add interconnect-names qup-core,qup-config and qup-memory to all qupv3
nodes.

Change-Id: I6cbed2a84fcd1ae7df96253121fc2dc735110b34
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-07-15 23:55:01 -07:00
Prakash Yadachi
839c5fe40d ARM: dts: qcom: Add ranges property for qupv3_0 node
Added ranges property for qupv3_0 node for Ravelin.

Change-Id: I441dc416c718f8da38a61fdd79c3ffbc676cbf14
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-07-11 10:45:18 +05:30
Prakash Yadachi
e3f1806765 ARM: dts: qcom: Update proper clock name
Update uart clock name from se to se-clk for Ravelin.

Change-Id: Ib2b614ba3a0f2bf307e7fa7678a10ccfe97da1c1
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-07-11 10:39:24 +05:30
Saranya R
a78b0ff36e ARM: dts: msm: Use "iommu-addresses" property for ravelin qup
Use upstream compatible DT property "iommu-addresses" instead
of "qcom,iommu-dma-addr-pool" for qup which describes the
addresses that qup cannot use.

Change-Id: I8912ee5a256a15ed8e0cb729dd784bce4568c4fb
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
2024-07-02 06:11:50 -07:00
Swetha Chikkaboraiah
1b78f8027a ARM: dts: msm: Add initial device tree for ravelin
Add initial device tree support for ravelin target.
This is a snapshot of dtsi files as of KP.1.0
'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom:
Disable cnss-kiwi SOL on anorak platform"")'.
Modified as per compilation and bootup.

Change-Id: Icb9a6e67879c68dbf894d1713fa2837882b9f00c
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
2024-06-11 23:43:27 -07:00