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ARM: dts: msm: Add support for graphics clock controller on KERA

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Add support for GPU clock controller and move corresponding
gdsc's from dummy to real on Kera platform.
While at it, add the clocks property to camera and display gdscs.

Change-Id: If3061a7603035e799e7548f0e2a93b7ded0e3005
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
This commit is contained in:
Anaadi Mishra
2024-07-23 16:36:11 +05:30
committed by Rohit Jadhav
parent 50eef2747b
commit ff82b07c78
1 changed files with 25 additions and 4 deletions
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29
qcom/kera.dtsi
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@@ -1845,8 +1845,17 @@
}; };
gpucc: clock-controller@3d90000 { gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc"; compatible = "qcom,kera-gpucc", "syscon";
clock-output-names = "gpucc_clocks"; reg = <0x3d90000 0xa000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
clock-names = "bi_tcxo",
"gpll0_out_main",
"gpll0_out_main_div";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -3079,26 +3088,32 @@
#include "ipcc-test-no-slpi.dtsi" #include "ipcc-test-no-slpi.dtsi"
&cam_cc_ipe_0_gdsc { &cam_cc_ipe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
status = "ok"; status = "ok";
}; };
&cam_cc_ofe_gdsc { &cam_cc_ofe_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
status = "ok"; status = "ok";
}; };
&cam_cc_tfe_0_gdsc { &cam_cc_tfe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
status = "ok"; status = "ok";
}; };
&cam_cc_tfe_1_gdsc { &cam_cc_tfe_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
status = "ok"; status = "ok";
}; };
&cam_cc_tfe_2_gdsc { &cam_cc_tfe_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
status = "ok"; status = "ok";
}; };
&cam_cc_titan_top_gdsc { &cam_cc_titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
interconnect-names = "mmnoc"; interconnect-names = "mmnoc";
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
@@ -3106,11 +3121,13 @@
}; };
&disp_cc_mdss_core_gdsc { &disp_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&disp_cc_mdss_core_int2_gdsc { &disp_cc_mdss_core_int2_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
@@ -3160,13 +3177,17 @@
}; };
&gpu_cc_cx_gdsc { &gpu_cc_cx_gdsc {
compatible = "regulator-fixed";
reg = <0x3d99110 0x4>; reg = <0x3d99110 0x4>;
parent-supply = <&VDD_CX_LEVEL>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
status = "ok"; status = "ok";
}; };
&gpu_cc_gx_gdsc { &gpu_cc_gx_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_GFX_LEVEL>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
status = "ok"; status = "ok";
}; };