ARM: dts: msm: add soccp dtsi property to sun target
This change adds the soccp phandle needed for SOCCP power vote for hw-fencing usecases. Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2 Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
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@@ -569,6 +569,8 @@ Optional properties:
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silver or gold or gold+.
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- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
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- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
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- qcom,sde-soccp-controller: The phandle for the soccp controller.
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This value is optional and only required for targets with SOCCP.
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- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
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- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
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for ipcc registers access.
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@@ -911,6 +913,7 @@ Example:
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-qos-cpu-irq-latency = <300>;
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qcom,sde-soccp-controller = <&soccp_pas>;
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qcom,sde-ipcc-protocol-id = <0x2>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
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@@ -265,6 +265,7 @@
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qcom,sde-ipcc-protocol-id = <0x4>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
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qcom,sde-soccp-controller = <&soccp_pas>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-reg-dma-off = <0 0x800>;
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