From febcd23b71babca9c5f838a7abdec2f1ca6acc75 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 11:33:00 -0800 Subject: [PATCH] ARM: dts: msm: add soccp dtsi property to sun target This change adds the soccp phandle needed for SOCCP power vote for hw-fencing usecases. Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 779a3da7..b334b16d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -569,6 +569,8 @@ Optional properties: silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. +- qcom,sde-soccp-controller: The phandle for the soccp controller. + This value is optional and only required for targets with SOCCP. - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. @@ -911,6 +913,7 @@ Example: qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 36d306c0..5d73da80 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,6 +265,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-soccp-controller = <&soccp_pas>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>;