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ARM: dts: msm: add soccp dtsi property to sun target

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This change adds the soccp phandle needed for SOCCP power vote for
hw-fencing usecases.

Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This commit is contained in:
Christina Oliveira
2024-01-24 11:33:00 -08:00
parent 745316e53e
commit febcd23b71
2 changed files with 4 additions and 0 deletions
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3
bindings/sde.txt
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@@ -569,6 +569,8 @@ Optional properties:
silver or gold or gold+. silver or gold or gold+.
- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
- qcom,sde-soccp-controller: The phandle for the soccp controller.
This value is optional and only required for targets with SOCCP.
- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
for ipcc registers access. for ipcc registers access.
@@ -911,6 +913,7 @@ Example:
qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-protocol-id = <0x2>;
qcom,sde-ipcc-client-dpu-phys-id = <0x19>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>;

1
display/sun-sde-common.dtsi
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@@ -265,6 +265,7 @@
qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-soccp-controller = <&soccp_pas>;
/* offsets are relative to "mdp_phys + qcom,sde-off */ /* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-off = <0 0x800>;