dt-bindings: pci: qcom: Add PCIe EP DT Bindings on sdxkova
Add PCIE endpoint related DT bindings on sdxkova. Change-Id: Ied1e29b5f272cd10b18334e710c611c407422c43 Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
This commit is contained in:
Anvita T
467
bindings/pci/qcom,msm-ep-pcie.yaml
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467
bindings/pci/qcom,msm-ep-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,msm-ep-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) MSM PCI express Endpoint Controller
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maintainers:
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- Anvita T <quic_atadepal@quicinc.com>
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properties:
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compatible:
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enum:
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- qcom,pcie-ep
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reg:
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minItems: 7
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items:
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- description: PCIe MSM MSI address reserved space
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- description: DesignWare PCIe core (dm_core) registers
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- description: External local bus interface (elbi) registers
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- description: Address Translation Unit (ATU) registers
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- description: PCIe MSM specific (parf) registers
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- description: PCIe Physical layer (phy) registers
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- description: BAR memory region
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- description: PCIe MSM MSI address reserved space for vf
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- description: DesignWare PCIe core (dm_core) registers for vf
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- description: DesignWare PCIe EDMA registers
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- description: Register to avoid device reset during host reboot
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- description: AOSS reset clear register
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- description: PCIe RUMI (rumi) registers
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reg-names:
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minItems: 7
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items:
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- const: msi
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- const: dm_core
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- const: elbi
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- const: iatu
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- const: parf
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- const: phy
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- const: mmio
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- const: msi_vf
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- const: dm_core_vf
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- const: edma
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- const: tcsr_pcie_perst_en
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- const: aoss_cc_reset
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- const: rumi
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interrupts:
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minItems: 1
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items:
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- description: PCIe Global interrupt
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- description: PCIe PME turnoff interrupt
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- description: PCIe Dstate change interrupt
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- description: PCIe L1ss timeout interrupt
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- description: PCIe Link up interrupt
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- description: PCIe Likk down interrupt
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- description: PCIe bridge flush interrupt
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- description: PCIe BME interrupt
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interrupt-names:
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minItems: 1
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items:
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- const: int_global
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- const: int_pm_turnoff
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- const: int_dstate_change
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- const: int_l1sub_timeout
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- const: int_link_up
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- const: int_link_down
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- const: int_bridge_flush_n
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- const: int_bme
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pinctrl-names:
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description: GPIO configuration at the init time.
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items:
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- const: default
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pinctrl-0:
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description: Should contain default pinctrl.
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perst-gpio:
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description: GPIO used as PERST# input signal
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maxItems: 1
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wake-gpio:
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description: GPIO used as WAKE# output signal
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maxItems: 1
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clkreq-gpio:
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description: GPIO used to wake system in L1ss sleep
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maxItems: 1
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mdm2apstatus-gpio:
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description: GPIO used to indicate mdm to ap status
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maxItems: 1
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gdsc-vdd-supply:
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description: A phandle to the core gdsc power supply
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gdsc-phy-vdd-supply:
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description: A phandle to the phy gdsc power supply
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vreg-1p2-supply:
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description: A phandle to the 1.2v power supply
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vreg-0p9-supply:
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description: A phandle to the 0.9v power supply
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vreg-qref-supply:
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description: A phandle to the qref power supply
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vreg-mx-supply:
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description: A phandle to the mx power supply
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vreg-cx-supply:
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description: A phandle to the cx power supply
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qcom,vreg-1p2-voltage-level:
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description: Array containing the min, max supported voltage and current for 1.2v power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-0p9-voltage-level:
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description: Array containing the min, max supported voltage and current for 0.9v power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-qref-voltage-level:
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description: Array containing the min, max supported voltage and current for qref power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: pcie_core_reset
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- const: pcie_phy_reset
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interconnects:
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maxItems: 1
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interconnect-names:
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items:
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- const: icc_path
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# Common definitions for clocks, clock-names and reset.
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# Platform constraints are described later.
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clocks:
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description: Phandles to the clocks.
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minItems: 1
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maxItems: 14
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anyOf:
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- items:
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- description: PCIe PIPE clock
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- description: PCIe reference clock source
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- description: PCIe Auxiliary clock
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- description: PCIe CFG AHB clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe low dropout regulator clock
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- description: PCIe Slave Q2A AXI clock
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- description: PCIe DDRS SF translational buffer unit clock
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- description: PCIe aggregation NoC AXI clock
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- description: PCIe CNOC SF AXI clock
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- description: PCIe Multiplexer clock for the PIPE clock
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- description: PCIe external source PIPE clock
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- description: PCIe PHY Auxiliary clock
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clock-names:
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description: Names of the clocks.
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minItems: 1
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maxItems: 14
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anyOf:
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- items:
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- const: pcie_pipe_clk
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- const: pcie_0_ref_clk_src
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- const: pcie_aux_clk
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- const: pcie_cfg_ahb_clk
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- const: pcie_mstr_axi_clk
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- const: pcie_slv_axi_clk
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- const: pcie_ldo
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- const: pcie_slv_q2a_axi_clk
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- const: pcie_ddrss_sf_tbu_clk
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- const: pcie_aggre_noc_0_axi_clk
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- const: gcc_cnoc_pcie_sf_axi_clk
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- const: pcie_pipe_clk_mux
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- const: pcie_pipe_clk_ext_src
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- const: pcie_phy_aux_clk
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qcom,pcie-vendor-id:
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description: Vendor ID of the endpoint to be exposed
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qcom,pcie-device-id:
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description: Device ID of the endpoint to be exposed
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qcom,pcie-link-speed:
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description: This will override the max Gen speed
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- 0x1 GEN1
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- 0x2 GEN2
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- 0x3 GEN3
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- 0x4 GEN4
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 3, 4]
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qcom,pcie-phy-ver:
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description: States the PCIe PHY HSR version.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,no-path-from-ipa-to-pcie:
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description: This will configure iatu for IPA transactions as there is no
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direct path from the IPA to PCIe.
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type: boolean
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qcom,pcie-aggregated-irq:
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description: This will configure iatu for IPA transactions as there is no
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direct path from the IPA to PCIe.
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type: boolean
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qcom,pcie-mhi-a7-irq:
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description: This will configure iatu for IPA transactions as there is no
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direct path from the IPA to PCIe.
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type: boolean
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qcom,tcsr-not-supported:
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description: This will configure iatu for IPA transactions as there is no
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direct path from the IPA to PCIe.
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type: boolean
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qcom,phy-status-reg2:
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description: Offset from PCIe PHY base to check the PCIe PHY status.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,mhi-soc-reset-offset:
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description: Offset from PCIe PHY base to check the PCIe PHY status.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,aux-clk:
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description: This sets the aux clock frequency value.
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$ref: /schemas/types.yaml#/definitions/uint32
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iommu-map:
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description: As described in the pci-iommu.txt.
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maxItems: 1
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qcom,phy-init:
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description: PCIe PHY initialization sequence.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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'#address-cells':
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description: Should provide a value of 0.
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$ref: /schemas/types.yaml#/definitions/uint32
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'#interrupt-cells':
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description: Should provide a value of 1.
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$ref: /schemas/types.yaml#/definitions/uint32
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'#interrupt-map-mask':
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description: should provide a value of 0xffffffff.
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$ref: /schemas/types.yaml#/definitions/uint32
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interrupt-map:
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description: Must create mapping for the number of interrupts
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that are defined in above interrupts property.
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For PCIe device node, it should define 6 mappings for
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the corresponding PCIe interrupts supporting the
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specification.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-mx-voltage-level:
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description: Support PCIe Gen4 on sdxlemur by scaling MX to
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appropriate voltage.
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$ref: /schemas/types.yaml#/definitions/uint32
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max-clock-frequency-hz:
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description: list of the maximum operating frequencies stored
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in the same order of clock names.
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qcom,tcsr-perst-separation-enable-offset:
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description: Offset for TCSR perst seperation enable.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,tcsr-reset-separation-offset:
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description: Offset for TCSR reset seperation.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,tcsr-perst-enable-offset:
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description: Offset for TCSR perst enable.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,tcsr-hot-reset-offset:
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description: Offset for TCSR hot reset enable.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,perst-raw-rst-status-b:
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description: Bit for perset raw reset status.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,dbi-base-reg:
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description: Register offset for DBI base address.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,slv-space-reg:
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description: Register offset for slave address space size.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-active-config:
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description: active configuration of PCIe addressing.
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type: boolean
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qcom,pcie-edma:
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description: edma usage for PCIe.
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type: boolean
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qcom,pcie-cesta-clkreq-offset:
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description: Offset from PCIe PARF base to PCIe CESTA CLKREQ register.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-perst-enum:
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description: Link enumeration will be triggered by PERST deassertion.
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type: boolean
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qcom,pcie-m2-autonomous:
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description: Enable L1ss sleep/exit to support M2 autonomous mode.
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type: boolean
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qcom,override-disable-sriov:
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description: Set to report as SRIOV capability disable with client (MHI) driver.
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type: boolean
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nvmem-cells:
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description: Phandle of nvmem cell containing the address for boot_config.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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nvmem-cell-names:
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description: nvmem cell name for boot_config.
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$ref: /schemas/types.yaml#/definitions/string-array
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qcom,fast-boot-mask:
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description: Bitmask to read fast_boot value from boot_config cell.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,host-bypass-mask:
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description: Bitmask to read host_bypass value from boot_config cell.
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Will work only when host_bypass is 1 bit in boot_config.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,fast-boot-values:
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description: fast_boot values to check against boot_config based value for confirming
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that host-interface is PCIe.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,ep-pcie-num-ipc-pages-dev-fac:
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description: If property is present reduce the ep pcie ipc logging size
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based on the divisor factor. This property also represents the divisor factor.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-sm-sequence:
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description: PCIe State Manager sequence.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,pcie-sm-branch-sequence:
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description: PCIe state manager branch sequence.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,pcie-sm-branch-offset:
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description: Offset from PCIe state manager base to load the branch sequence.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-sm-start-offset:
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description: Offset from PCIe state manager base to start/enable the state manager.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-disconnect-req-reg-b:
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description: It specifies the register responsible for handling PCIe disconnect requests.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,aoss-rst-clr:
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description: If present, indicates that the reset clear signal is enabled.
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It is used to clear and write reset signals to the specified register within the AOSS.
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type: boolean
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- pinctrl-names
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- pinctrl-0
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- perst-gpio
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- wake-gpio
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- resets
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- reset-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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pcie_ep: qcom,pcie@bfffd000 {
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compatible = "qcom,pcie-ep";
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reg = <0xbfffd000 0x1000>,
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<0xbfffe000 0x1000>,
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<0xbffff000 0x1000>,
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<0xfc520000 0x2000>,
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<0xfc526000 0x1000>,
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<0xfc527000 0x1000>,
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<0x01fcb000 0x1000>;
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reg-names = "msi", "dm_core", "elbi", "parf", "phy", "mmio",
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"tcsr_pcie_perst";
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#address-cells = <0>;
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interrupt-parent = <&pcie_ep>;
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interrupts = <0 1 2 3 4 5>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 44 0
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1 &intc 0 46 0
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2 &intc 0 47 0
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3 &intc 0 50 0
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4 &intc 0 51 0
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5 &intc 0 52 0>;
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interrupt-names = "int_pm_turnoff", "int_dstate_change",
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"int_l1sub_timeout", "int_link_up",
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"int_link_down", "int_bridge_flush_n";
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perst-gpio = <&msmgpio 65 0>;
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wake-gpio = <&msmgpio 61 0>;
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clkreq-gpio = <&msmgpio 64 0>;
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mdm2apstatus-gpio = <&tlmm_pinmux 16 0>;
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gdsc-vdd-supply = <&gdsc_pcie_0>;
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vreg-1.8-supply = <&pmd9635_l8>;
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vreg-0.9-supply = <&pmd9635_l4>;
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qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
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qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
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clock-names = "pcie_pipe_clk",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_ldo";
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max-clock-frequency-hz = <62500000>, <1000000>,
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<0>, <0>, <0>, <0>;
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resets = <&clock_gcc GCC_PCIE_BCR>,
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<&clock_gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_core_reset", "pcie_phy_reset";
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qcom,pcie-link-speed = <1>;
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qcom,pcie-active-config;
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qcom,pcie-aggregated-irq;
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qcom,pcie-mhi-a7-irq;
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qcom,pcie-perst-enum;
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qcom,phy-status-reg = <0x728>;
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qcom,dbi-base-reg = <0x168>;
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qcom,slv-space-reg = <0x16c>;
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qcom,phy-init = <0x604 0x03 0x0 0x1
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0x048 0x08 0x0 0x1
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0x64c 0x4d 0x0 0x1
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0x600 0x00 0x0 0x1
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};
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