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ARM: dts: msm: add tgu for ipcb/spmi on sun

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Add tgu node for ipcb and spmi0/1 on sun.

Change-Id: Ia4468b846f64b8812ac43e4d2aeb31a223dea64f
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
This commit is contained in:
Yuanfang Zhang
2023-12-21 18:48:46 +08:00
parent 43823e428c
commit f82fac6ae3
1 changed files with 52 additions and 0 deletions
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52
qcom/sun-coresight.dtsi
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@@ -4,6 +4,58 @@
*/
&soc {
ipcb_tgu: tgu@10b0e000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb999>;
reg = <0x10b0e000 0x1000>;
reg-names = "tgu-base";
tgu-steps = <3>;
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-timer-counters = <8>;
coresight-name = "coresight-tgu-ipcb";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
spmi_tgu0: tgu@10b0f000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb999>;
reg = <0x10b0f000 0x1000>;
reg-names = "tgu-base";
tgu-steps = <3>;
tgu-conditions = <4>;
tgu-regs = <9>;
tgu-timer-counters = <8>;
coresight-name = "coresight-tgu-spmi0";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
spmi_tgu1: tgu@10b10000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb999>;
reg = <0x10b10000 0x1000>;
reg-names = "tgu-base";
tgu-steps = <3>;
tgu-conditions = <4>;
tgu-regs = <9>;
tgu-timer-counters = <8>;
coresight-name = "coresight-tgu-spmi1";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
csr: csr@10001000 {
compatible = "qcom,coresight-csr";
reg = <0x10001000 0x1000>;