samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: Add CRMV regs disp, camera and pcie on sun

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CRMV regs have status captured for various commands/voltage levels.
Map CRMV registers in device so that driver can dump them when required.

Change-Id: I05911a0646b2317f90fd425e172d0458ce669ab0
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
This commit is contained in:
Minghao Zhang
2023-12-26 12:46:49 +05:30
parent bdae31f18b
commit f3bd05ce44
1 changed files with 9 additions and 6 deletions
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15
qcom/sun.dtsi
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@@ -1294,8 +1294,9 @@
disp_crm: crm@af21000 {
label = "disp_crm";
compatible = "qcom,disp-crm-v2";
reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>, <0xaf29f00 0x100>;
reg-names = "base", "crm_b", "crm_c", "common";
reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>,
<0xaf29800 0x700>, <0xaf29f00 0x100>;
reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "disp_crm_drv0";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
@@ -1306,8 +1307,9 @@
cam_crm: crm@adcb000 {
label = "cam_crm";
compatible = "qcom,cam-crm-v2";
reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>, <0xadcfd00 0x100>;
reg-names = "base", "crm_b", "crm_c", "common";
reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>,
<0xadcf600 0x700>, <0xadcfd00 0x100>;
reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
interrupts = <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cam_crm_drv0";
clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
@@ -1318,8 +1320,9 @@
pcie_crm: crm@1d01000 {
label = "pcie_crm";
compatible = "qcom,pcie-crm-v2";
reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>, <0x1d05f00 0x100>;
reg-names = "base", "crm_b", "crm_c", "common";
reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>,
<0x1d05800 0x700>, <0x1d05f00 0x100>;
reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
interrupts = <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pcie_crm_drv0";
clocks = <&pcie_0_pipe_clk>;