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Merge "ARM: dts: msm: Add support for Tuna7 GPU"

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QCTECMDR Service
2025-01-10 03:47:30 -08:00
committed by Gerrit - the friendly Code Review server
parent ffeafa69e7 af0e7a0660
commit f2fb83454b
5 changed files with 352 additions and 84 deletions
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3
Kbuild
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@@ -9,7 +9,8 @@ dtbo-y += gpu/sun-gpu.dtbo \
endif endif
ifeq ($(CONFIG_ARCH_TUNA), y) ifeq ($(CONFIG_ARCH_TUNA), y)
dtbo-y += gpu/tuna-gpu.dtbo dtbo-y += gpu/tuna-gpu.dtbo \
gpu/tuna7-gpu.dtbo
endif endif
ifeq ($(CONFIG_ARCH_KERA), y) ifeq ($(CONFIG_ARCH_KERA), y)

390
gpu/tuna-gpu-pwrlevels.dtsi
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@@ -5,111 +5,335 @@
&msm_gpu { &msm_gpu {
/* Power levels */ /* Power levels */
qcom,initial-pwrlevel = <8>; qcom,gpu-pwrlevel-bins {
qcom,gpu-pwrlevels {
compatible="qcom,gpu-pwrlevels";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
/* Turbo_L1 */ compatible = "qcom,gpu-pwrlevels-bins";
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>; /*
qcom,bus-min = <11>; * The bins need to match based on speed bin first and then SKU.
qcom,bus-max = <11>; * Keep pwrlevel bins sorted in ascending order of the fmax of the bins.
*/
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <8>;
qcom,speed-bin = <0>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <510000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <362000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <264000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
}; };
/* Turbo */ qcom,gpu-pwrlevels-1 {
qcom,gpu-pwrlevel@1 { #address-cells = <1>;
reg = <1>; #size-cells = <0>;
qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>; qcom,initial-pwrlevel = <8>;
qcom,bus-min = <9>; qcom,speed-bin = <0xd8>;
qcom,bus-max = <10>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1025000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <510000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <362000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <264000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
}; };
/* Nom_L1 */ qcom,gpu-pwrlevels-2 {
qcom,gpu-pwrlevel@2 { #address-cells = <1>;
reg = <2>; #size-cells = <0>;
qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>; qcom,initial-pwrlevel = <8>;
qcom,bus-min = <7>; qcom,speed-bin = <0xf2>;
qcom,bus-max = <9>;
};
/* Nom */ /* Turbo_L1 */
qcom,gpu-pwrlevel@3 { qcom,gpu-pwrlevel@0 {
reg = <3>; reg = <0>;
qcom,gpu-freq = <763000000>; qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <8>; qcom,bus-freq = <11>;
qcom,bus-min = <7>; qcom,bus-min = <11>;
qcom,bus-max = <9>; qcom,bus-max = <11>;
}; };
/* SVS_L2 */ /* Turbo */
qcom,gpu-pwrlevel@4 { qcom,gpu-pwrlevel@1 {
reg = <4>; reg = <1>;
qcom,gpu-freq = <688000000>; qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>; qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <6>; qcom,bus-freq = <10>;
qcom,bus-min = <4>; qcom,bus-min = <9>;
qcom,bus-max = <7>; qcom,bus-max = <10>;
}; };
/* SVS_L1 */ /* Nom_L1 */
qcom,gpu-pwrlevel@5 { qcom,gpu-pwrlevel@2 {
reg = <5>; reg = <2>;
qcom,gpu-freq = <644000000>; qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <6>; qcom,bus-freq = <9>;
qcom,bus-min = <4>; qcom,bus-min = <7>;
qcom,bus-max = <7>; qcom,bus-max = <9>;
}; };
/* SVS */ /* Nom */
qcom,gpu-pwrlevel@6 { qcom,gpu-pwrlevel@3 {
reg = <6>; reg = <3>;
qcom,gpu-freq = <510000000>; qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <4>; qcom,bus-freq = <8>;
qcom,bus-min = <2>; qcom,bus-min = <7>;
qcom,bus-max = <6>; qcom,bus-max = <9>;
}; };
/* Low_SVS */ /* SVS_L2 */
qcom,gpu-pwrlevel@7 { qcom,gpu-pwrlevel@4 {
reg = <7>; reg = <4>;
qcom,gpu-freq = <362000000>; qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <3>; qcom,bus-freq = <6>;
qcom,bus-min = <1>; qcom,bus-min = <4>;
qcom,bus-max = <3>; qcom,bus-max = <7>;
}; };
/* Low_SVS_D1 */ /* SVS_L1 */
qcom,gpu-pwrlevel@8 { qcom,gpu-pwrlevel@5 {
reg = <8>; reg = <5>;
qcom,gpu-freq = <264000000>; qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <1>; qcom,bus-freq = <6>;
qcom,bus-min = <1>; qcom,bus-min = <4>;
qcom,bus-max = <3>; qcom,bus-max = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <510000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <362000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <264000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
}; };
}; };
}; };

3
gpu/tuna-gpu.dtsi
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@@ -65,6 +65,9 @@
<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */ <MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L2 index=11 */ <MHZ_TO_KBPS(4761, 4)>; /* TURBO_L2 index=11 */
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
zap-shader { zap-shader {
memory-region = <&gpu_microcode_mem>; memory-region = <&gpu_microcode_mem>;
}; };

30
gpu/tuna7-gpu.dts Normal file
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@@ -0,0 +1,30 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/clock/qcom,gpucc-tuna.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,tuna.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include "tuna-gpu.dtsi"
#include "tuna-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. tuna7 SoC";
compatible = "qcom,tuna";
qcom,msm-id = <0x2a9 0x10000>;
qcom,board-id = <0 0>;
};
&msm_gpu {
/delete-property/qcom,gpu-model;
qcom,gpu-model = "Adreno822";
};

10
gpu/tuna7-gpu.dtsi Normal file
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@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-gpu.dtsi"
&msm_gpu {
qcom,gpu-model = "Adreno822";
};