From af0e7a0660bfbe4c218711f0776c9e7b1f45fcc6 Mon Sep 17 00:00:00 2001
From: SIVA MULLATI <quic_smullati@quicinc.com>
Date: Wed, 13 Nov 2024 20:06:34 +0530
Subject: [PATCH] ARM: dts: msm: Add support for Tuna7 GPU

Add initial support for Tuna7 GPU in the devicetree.

Change-Id: I66ac7382ce0dfc10291a2318e0da3d9880c24790
Signed-off-by: SIVA MULLATI <quic_smullati@quicinc.com>
---
 Kbuild                      |   3 +-
 gpu/tuna-gpu-pwrlevels.dtsi | 390 ++++++++++++++++++++++++++++--------
 gpu/tuna-gpu.dtsi           |   3 +
 gpu/tuna7-gpu.dts           |  30 +++
 gpu/tuna7-gpu.dtsi          |  10 +
 5 files changed, 352 insertions(+), 84 deletions(-)
 create mode 100644 gpu/tuna7-gpu.dts
 create mode 100644 gpu/tuna7-gpu.dtsi

diff --git a/Kbuild b/Kbuild
index eef19472..d56aed40 100644
--- a/Kbuild
+++ b/Kbuild
@@ -9,7 +9,8 @@ dtbo-y += gpu/sun-gpu.dtbo \
 endif
 
 ifeq ($(CONFIG_ARCH_TUNA), y)
-dtbo-y += gpu/tuna-gpu.dtbo
+dtbo-y += gpu/tuna-gpu.dtbo \
+		gpu/tuna7-gpu.dtbo
 endif
 
 always-y    := $(dtb-y) $(dtbo-y)
diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi
index 8294ea31..5d8edc86 100644
--- a/gpu/tuna-gpu-pwrlevels.dtsi
+++ b/gpu/tuna-gpu-pwrlevels.dtsi
@@ -5,111 +5,335 @@
 
 &msm_gpu {
 	/* Power levels */
-	qcom,initial-pwrlevel = <8>;
-
-	qcom,gpu-pwrlevels {
-		compatible="qcom,gpu-pwrlevels";
-
+	qcom,gpu-pwrlevel-bins {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		/* Turbo_L1 */
-		qcom,gpu-pwrlevel@0 {
-			reg = <0>;
-			qcom,gpu-freq = <1050000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+		compatible = "qcom,gpu-pwrlevels-bins";
 
-			qcom,bus-freq = <11>;
-			qcom,bus-min = <11>;
-			qcom,bus-max = <11>;
+		/*
+		 * The bins need to match based on speed bin first and then SKU.
+	         * Keep pwrlevel bins sorted in ascending order of the fmax of the bins.
+		 */
+		qcom,gpu-pwrlevels-0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <8>;
+			qcom,speed-bin = <0>;
+
+			/* Turbo_L1 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+			};
+
+			/* Turbo */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <937000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <9>;
+				qcom,bus-max = <10>;
+			};
+
+			/* Nom_L1 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <873000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq = <9>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+			};
+
+			/* Nom */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+			};
+
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+			};
 		};
 
-		/* Turbo */
-		qcom,gpu-pwrlevel@1 {
-			reg = <1>;
-			qcom,gpu-freq = <937000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+		qcom,gpu-pwrlevels-1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			qcom,bus-freq = <10>;
-			qcom,bus-min = <9>;
-			qcom,bus-max = <10>;
+			qcom,initial-pwrlevel = <8>;
+			qcom,speed-bin = <0xd8>;
+
+			/* Turbo_L1 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1025000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+			};
+
+			/* Turbo */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <937000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <9>;
+				qcom,bus-max = <10>;
+			};
+
+			/* Nom_L1 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <873000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq = <9>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+			};
+
+			/* Nom */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+			};
+
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+			};
 		};
 
-		/* Nom_L1 */
-		qcom,gpu-pwrlevel@2 {
-			reg = <2>;
-			qcom,gpu-freq = <873000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+		qcom,gpu-pwrlevels-2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			qcom,bus-freq = <9>;
-			qcom,bus-min = <7>;
-			qcom,bus-max = <9>;
-		};
+			qcom,initial-pwrlevel = <8>;
+			qcom,speed-bin = <0xf2>;
 
-		/* Nom */
-		qcom,gpu-pwrlevel@3 {
-			reg = <3>;
-			qcom,gpu-freq = <763000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+			/* Turbo_L1 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 
-			qcom,bus-freq = <8>;
-			qcom,bus-min = <7>;
-			qcom,bus-max = <9>;
-		};
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+			};
 
-		/* SVS_L2 */
-		qcom,gpu-pwrlevel@4 {
-			reg = <4>;
-			qcom,gpu-freq = <688000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+			/* Turbo */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <937000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
 
-			qcom,bus-freq = <6>;
-			qcom,bus-min = <4>;
-			qcom,bus-max = <7>;
-		};
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <9>;
+				qcom,bus-max = <10>;
+			};
 
-		/* SVS_L1 */
-		qcom,gpu-pwrlevel@5 {
-			reg = <5>;
-			qcom,gpu-freq = <644000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+			/* Nom_L1 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <873000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
-			qcom,bus-freq = <6>;
-			qcom,bus-min = <4>;
-			qcom,bus-max = <7>;
-		};
+				qcom,bus-freq = <9>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+			};
 
-		/* SVS */
-		qcom,gpu-pwrlevel@6 {
-			reg = <6>;
-			qcom,gpu-freq = <510000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+			/* Nom */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
-			qcom,bus-freq = <4>;
-			qcom,bus-min = <2>;
-			qcom,bus-max = <6>;
-		};
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+			};
 
-		/* Low_SVS */
-		qcom,gpu-pwrlevel@7 {
-			reg = <7>;
-			qcom,gpu-freq = <362000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
-			qcom,bus-freq = <3>;
-			qcom,bus-min = <1>;
-			qcom,bus-max = <3>;
-		};
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
 
-		/* Low_SVS_D1 */
-		qcom,gpu-pwrlevel@8 {
-			reg = <8>;
-			qcom,gpu-freq = <264000000>;
-			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
-			qcom,bus-freq = <1>;
-			qcom,bus-min = <1>;
-			qcom,bus-max = <3>;
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+			};
 		};
 	};
 };
diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi
index c56c55ff..2adffa7d 100644
--- a/gpu/tuna-gpu.dtsi
+++ b/gpu/tuna-gpu.dtsi
@@ -62,6 +62,9 @@
 		<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
 		<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L2 index=11 */
 
+	nvmem-cells = <&gpu_speed_bin>;
+	nvmem-cell-names = "speed_bin";
+
 	zap-shader {
 		memory-region = <&gpu_microcode_mem>;
 	};
diff --git a/gpu/tuna7-gpu.dts b/gpu/tuna7-gpu.dts
new file mode 100644
index 00000000..5e5ce5e9
--- /dev/null
+++ b/gpu/tuna7-gpu.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-tuna.h>
+#include <dt-bindings/clock/qcom,gpucc-tuna.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,tuna.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+#include "tuna-gpu.dtsi"
+#include "tuna-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. tuna7 SoC";
+	compatible = "qcom,tuna";
+	qcom,msm-id = <0x2a9 0x10000>;
+	qcom,board-id = <0 0>;
+};
+
+&msm_gpu {
+	/delete-property/qcom,gpu-model;
+        qcom,gpu-model = "Adreno822";
+};
diff --git a/gpu/tuna7-gpu.dtsi b/gpu/tuna7-gpu.dtsi
new file mode 100644
index 00000000..2a286fac
--- /dev/null
+++ b/gpu/tuna7-gpu.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "tuna-gpu.dtsi"
+
+&msm_gpu {
+	qcom,gpu-model = "Adreno822";
+};