samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge "ARM: dts: msm: Adding Regulator support for both HS and SS Phy"

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QCTECMDR Service
2024-10-22 16:01:23 -07:00
committed by Gerrit - the friendly Code Review server
parent ed1f7c3a3e a3e441feb2
commit f2b225e5a5
1 changed files with 16 additions and 5 deletions
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21
qcom/tuna-usb.dtsi
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@@ -37,11 +37,6 @@
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
qcom,use-pdc-interrupts;
qcom,use-eusb2-phy;
@@ -49,6 +44,20 @@
qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
dwc3_0: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0x0 0xa600000 0x0 0xd93c>;
@@ -92,6 +101,7 @@
vdd-supply = <&L3B>;
qcom,vdd-voltage-level = <0 880000 880000>;
vdda12-supply = <&L4B>;
vdd_refgen-supply = <&L2B>;
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
@@ -116,6 +126,7 @@
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L4B>;
vdd_refgen-supply = <&L2B>;
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,