samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge "ARM: dts: msm: tuna: Update capacity property"

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QCTECMDR Service
2024-10-11 17:24:10 -07:00
committed by Gerrit - the friendly Code Review server
parent 9add7d4bd1 90b3ccd884
commit f26c6744fd
1 changed files with 6 additions and 6 deletions
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qcom/tuna.dtsi
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@@ -143,7 +143,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_2: l2-cache { L2_2: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -164,7 +164,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_3: l2-cache { L2_3: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -185,7 +185,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_4>; next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_4: l2-cache { L2_4: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -206,7 +206,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_5>; next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_5: l2-cache { L2_5: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -227,7 +227,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_6: l2-cache { L2_6: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -248,7 +248,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_7>; next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1300>; capacity-dmips-mhz = <1178>;
dynamic-power-coefficient = <295>; dynamic-power-coefficient = <295>;
L2_7: l2-cache { L2_7: l2-cache {
compatible = "cache"; compatible = "cache";