From 90b3ccd884d20f5a969f765a2301fa25c91368cf Mon Sep 17 00:00:00 2001
From: Ankit Sharma <quic_anshar@quicinc.com>
Date: Tue, 8 Oct 2024 12:23:50 +0530
Subject: [PATCH] ARM: dts: msm: tuna: Update capacity property

Update "capacity-dmips-mhz" for tuna. It is used to build Energy Model
which in turn is used by EAS to take placement decisions.

Change-Id: I7e0ad3f42d39303e044b6fbc7cfd3f76492d09de
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
---
 qcom/tuna.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index ede3e8d1..5c33023c 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -137,7 +137,7 @@
 			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_2>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_2: l2-cache {
 			      compatible = "cache";
@@ -156,7 +156,7 @@
 			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_3>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_3: l2-cache {
 			      compatible = "cache";
@@ -175,7 +175,7 @@
 			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_4>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_4: l2-cache {
 			      compatible = "cache";
@@ -194,7 +194,7 @@
 			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_5>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_5: l2-cache {
 			      compatible = "cache";
@@ -213,7 +213,7 @@
 			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_6>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_6: l2-cache {
 			      compatible = "cache";
@@ -232,7 +232,7 @@
 			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_7>;
-			capacity-dmips-mhz = <1300>;
+			capacity-dmips-mhz = <1178>;
 			dynamic-power-coefficient = <295>;
 			L2_7: l2-cache {
 			      compatible = "cache";