Merge "ARM: dts: msm: Fix the base addresses of LLCC banks for Pineapple SoC"

This commit is contained in:
qctecmdr
2023-10-06 09:44:22 -07:00
committed by Gerrit - the friendly Code Review server

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@@ -1816,8 +1816,11 @@
cache-controller@25000000 {
compatible = "qcom,pineapple-llcc", "qcom,llcc-v50";
reg = <0x25000000 0x800000> , <0x25800000 0x200000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg = <0x25000000 0x200000>, <0x25400000 0x200000>,
<0x25200000 0x200000>, <0x25600000 0x200000>,
<0x25800000 0x200000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse;