Add 'qcom/graphics/' from GRAPHICS.LA.15.0.r1-06300-pakala.0 of https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-devicetree
git-subtree-dir: qcom/graphics git-subtree-mainline:2bb579edb5git-subtree-split:96de6303a2
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kmiit
186
qcom/graphics/gpu/kera-gpu.dtsi
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186
qcom/graphics/gpu/kera-gpu.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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/* ACD Control register values */
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#define ACD_LEVEL_Turbo_L2 0xa8295ffd
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#define ACD_LEVEL_Turbo_L1 0xa82a5ffd
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#define ACD_LEVEL_Turbo 0x882c5ffd
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#define ACD_LEVEL_Nominal_L1 0x882d5ffd
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#define ACD_LEVEL_Nominal 0x882d5ffd
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#define ACD_LEVEL_SVS_L2 0xa82d5ffd
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#define ACD_LEVEL_SVS_L1 0x882f5ffd
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#define ACD_LEVEL_SVS 0Xc02d5ffd
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#define ACD_LEVEL_LowSVS 0Xc82f5ffd
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#define ACD_LEVEL_LowSVS_D1 0Xc82f5ffd
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&msm_gpu {
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compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0";
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status = "ok";
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reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>,
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<0x3d61000 0x800>, <0x3d9e000 0x1000>,
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<0x10048000 0x8000>, <0x10900000 0x80000>,
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<0x10b05000 0x1000>;
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reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc",
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"cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 286 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
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resets = <&gpucc GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
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reset-names = "freq_limiter_irq_clear";
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clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>;
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clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb",
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"gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk";
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <4>;
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qcom,tzone-names = "gpuss-0", "gpuss-1";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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qcom,bus-table-ddr7 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* LowSVS index=1 */
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<MHZ_TO_KBPS(451, 4)>, /* LowSVS index=2 */
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<MHZ_TO_KBPS(547, 4)>, /* LowSVS index=3 */
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<MHZ_TO_KBPS(681, 4)>, /* SVS index=4 */
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<MHZ_TO_KBPS(768, 4)>, /* SVS index=5 */
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<MHZ_TO_KBPS(1017, 4)>, /* SVS index=6 */
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<MHZ_TO_KBPS(1353, 4)>, /* NOM index=7 */
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<MHZ_TO_KBPS(1555, 4)>, /* NOM index=8 */
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<MHZ_TO_KBPS(1708, 4)>, /* TURBO index=9 */
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<MHZ_TO_KBPS(2092, 4)>; /* TURBO_L1 index=10 */
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qcom,bus-table-ddr8 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* LowSVS index=1 */
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<MHZ_TO_KBPS(547, 4)>, /* LowSVS index=2 */
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<MHZ_TO_KBPS(1353, 4)>, /* LowSVS index=3 */
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<MHZ_TO_KBPS(1555, 4)>, /* SVS index=4 */
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<MHZ_TO_KBPS(1708, 4)>, /* SVS index=5 */
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<MHZ_TO_KBPS(2092, 4)>, /* SVS index=6 */
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<MHZ_TO_KBPS(2736, 4)>, /* NOM index=7 */
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<MHZ_TO_KBPS(3187, 4)>, /* TURBO index=8 */
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<MHZ_TO_KBPS(3686, 4)>, /* TURBO index=9 */
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<MHZ_TO_KBPS(4224, 4)>; /* TURBO_L1 index=10 */
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nvmem-cells = <&gpu_gaming_bin>;
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nvmem-cell-names = "gaming_bin";
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 128K Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <131072>;
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qcom,mempool-reserved = <128>;
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};
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/* 256K Page Pool configuration */
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qcom,gpu-mempool@4 {
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reg = <4>;
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qcom,mempool-page-size = <262144>;
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qcom,mempool-reserved = <80>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@5 {
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reg = <5>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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};
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&soc {
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kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x3da0000 0x40000>;
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power-domains = <&gpucc GPU_CC_CX_GDSC>;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0 0x000>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2 0x000>;
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qcom,iommu-dma = "disabled";
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};
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};
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gmu: qcom,gmu@3d68000 {
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compatible = "qcom,gen7-gmu";
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reg = <0x3d68000 0x37000>, <0xb290000 0x10000>, <0x3d40000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
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interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
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<0 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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power-domains = <&gpucc GPU_CC_CX_GDSC>,
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<&gpucc GPU_CC_CX_GMU_GDSC>,
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<&gpucc GPU_CC_GX_GDSC>;
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power-domain-names = "cx", "gmu_cx", "gx";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "gmu_clk", "cxo_clk", "axi_clk",
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"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote";
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qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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<550000000 RPMH_REGULATOR_LEVEL_SVS>;
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iommus = <&kgsl_smmu 0x5 0x000>;
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qcom,iommu-dma = "disabled";
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mboxes = <&qmp_aop 0>;
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mbox-names = "aop";
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};
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};
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