From 994933d50b8f442c69283a1fef94ed1968f52908 Mon Sep 17 00:00:00 2001 From: Gerrit SelfHelp Service Account Date: Tue, 8 Aug 2023 01:08:53 -0700 Subject: [PATCH 001/113] Initial empty repository From 63075d8f6348beace36dbccef7fd49d63d612c84 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Wed, 23 Aug 2023 17:01:48 -0700 Subject: [PATCH 002/113] ARM: dts: msm: Initial commit for Adreno GPU Add initial Adreno GPU devicetree files. Change-Id: I460cc1d37a49b2b92d55fd6426d51bcb629fcdf5 Signed-off-by: Hareesh Gundu --- Kbuild | 8 + Makefile | 9 + bindings/adreno-busmon.txt | 16 + bindings/adreno-gmu.txt | 115 +++++ bindings/adreno-iommu.txt | 81 ++++ bindings/adreno-pwrlevels.txt | 94 ++++ bindings/adreno.txt | 528 +++++++++++++++++++++ gpu/pineapple-gpu-pwrlevels.dtsi | 687 ++++++++++++++++++++++++++++ gpu/pineapple-gpu.dts | 27 ++ gpu/pineapple-gpu.dtsi | 260 +++++++++++ gpu/pineapple-v2-gpu-pwrlevels.dtsi | 181 ++++++++ gpu/pineapple-v2-gpu.dts | 26 ++ gpu/pineapple-v2-gpu.dtsi | 14 + 13 files changed, 2046 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 bindings/adreno-busmon.txt create mode 100644 bindings/adreno-gmu.txt create mode 100644 bindings/adreno-iommu.txt create mode 100644 bindings/adreno-pwrlevels.txt create mode 100644 bindings/adreno.txt create mode 100644 gpu/pineapple-gpu-pwrlevels.dtsi create mode 100644 gpu/pineapple-gpu.dts create mode 100644 gpu/pineapple-gpu.dtsi create mode 100644 gpu/pineapple-v2-gpu-pwrlevels.dtsi create mode 100644 gpu/pineapple-v2-gpu.dts create mode 100644 gpu/pineapple-v2-gpu.dtsi diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..2ef6de5a --- /dev/null +++ b/Kbuild @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_ARCH_PINEAPPLE), y) +dtbo-y += gpu/pineapple-gpu.dtbo \ + gpu/pineapple-v2-gpu.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/bindings/adreno-busmon.txt b/bindings/adreno-busmon.txt new file mode 100644 index 00000000..b4d0757e --- /dev/null +++ b/bindings/adreno-busmon.txt @@ -0,0 +1,16 @@ +Adreno bus monitor device + +kgsl-busmon is a pseudo device that represents a devfreq bus bandwidth +governor. If this device is present then two different governors are used +for GPU DCVS and bus DCVS. + +Required properties: +- compatible: Must be "qcom,kgsl-busmon" +- label: Device name used for sysfs entry. + +Example: + +qcom,kgsl-busmon { + compatible = "qcom,kgsl-busmon"; + label = "kgsl-busmon"; +}; diff --git a/bindings/adreno-gmu.txt b/bindings/adreno-gmu.txt new file mode 100644 index 00000000..a5544793 --- /dev/null +++ b/bindings/adreno-gmu.txt @@ -0,0 +1,115 @@ +Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU) + +Required properties: +- compatible : + - "qcom,gpu-gmu" + - "qcom,gpu-gmu-hwsched" + - "qcom,gpu-rgmu" + - "qcom,gen7-gmu" + - "qcom,gen7-gmu-hwsched" +- reg: Specifies the GMU register base address and size. +- reg-names: Resource names used for the physical address + and length of GMU registers. +- interrupts: Interrupt mapping for GMU and HFI IRQs. +- interrupt-names: String property to describe the name of each interrupt. + +Bus Scaling Data: +qcom,msm-bus,name: String property to describe the name of bus client. +qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property. +qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase. +qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is: + , , // For Bus Scaling Usecase 1 + , , // For Bus Scaling Usecase 2 + <.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n + This property is a series of all vectors for all Bus Scaling Usecases. + Each set of vectors for each usecase describes bandwidth votes for a combination + of src/dst ports. The driver will set the desired use case based on the selected + power level and the desired bandwidth vote will be registered for the port pairs. + +GMU GDSC/regulators: +- regulator-names: List of regulator name strings +- vddcx-supply: Phandle for vddcx regulator device node. +- vdd-supply: Phandle for vdd regulator device node. + +- clock: List of clocks to be used for GMU register access and DCVS. See + Documentation/devicetree/bindings/clock/clock-bindings.txt + for information about the format. For each clock specified + here, there must be a corresponding entry in clock-names + (see below). + +- clock-names: List of clock names corresponding to the clocks specified in + the "clocks" property (above). See + Documentation/devicetree/bindings/clock/clock-bindings.txt + for more info. Currently GMU required these clock names: + "gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk", + "rbcpr_clk" + +- qcom,gmu-freq-table: List of frequencies the GMU clock can run at with their corresponding + voltage levels. + +- List of sub nodes, one for each of the translation context banks needed + for GMU to access system memory in different operating mode. Currently + supported names are: + - gmu_user: used for GMU 'user' mode address space. + - gmu_kernel: used for GMU 'kernel' mode address space. + Each sub node has the following required properties: + + - compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb" + - iommus : Specifies the SID's used by this context bank, this + needs to be pair, kgsl_smmu is the string + parsed by iommu driver to match this context bank with the + kgsl_smmu device defined in iommu device tree. On targets + where the msm iommu driver is used rather than the arm smmu + driver, this property may be absent. + +- qcom,ipc-core: + baseAddr - base address of the IPC region + size - size of the IPC region + + +Example: + +gmu: qcom,gmu@2c6a000 { + label = "kgsl-gmu"; + compatible = "qcom,gpu-gmu"; + + reg = <0x2c6a000 0x30000>; + reg-names = "kgsl_gmu_reg"; + + interrupts = <0 304 0>, <0 305 0>; + interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq"; + + qcom,msm-bus,name = "cnoc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 10036 0 0>, // CNOC off + <26 10036 0 100>; // CNOC on + + regulator-name = "vddcx", "vdd"; + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&clock_gpugcc clk_gcc_gmu_clk>, + <&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_RBCPR_CLK>; + + clock-names = "gmu_clk", "ahb_clk", "cxo_clk", + "axi_clk", "memnoc_clk", "rbcpr_clk"; + + qcom,gmu-freq-table = <200000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <500000000 RPMH_REGULATOR_LEVEL_SVS>; + + gmu_user: gmu_user { + compatible = "qcom,smmu-gmu-user-cb"; + iommus = <&kgsl_smmu 4>; + }; + + gmu_kernel: gmu_kernel { + compatible = "qcom,smmu-gmu-kernel-cb"; + iommus = <&kgsl_smmu 5>; + }; +}; diff --git a/bindings/adreno-iommu.txt b/bindings/adreno-iommu.txt new file mode 100644 index 00000000..fef7515c --- /dev/null +++ b/bindings/adreno-iommu.txt @@ -0,0 +1,81 @@ +Qualcomm Technologies, Inc. GPU IOMMU + +Required properties: + +Required properties: +- compatible : one of: + - "qcom,kgsl-smmu-v1" + - "qcom,kgsl-smmu-v2" + +- reg : Base address and size of the SMMU. + +- clocks : List of clocks to be used during SMMU register access. See + Documentation/devicetree/bindings/clock/clock-bindings.txt + for information about the format. For each clock specified + here, there must be a corresponding entry in clock-names + (see below). + +- clock-names : List of clock names corresponding to the clocks specified in + the "clocks" property (above). See + Documentation/devicetree/bindings/clock/clock-bindings.txt + for more info. +- qcom,protect : The GPU register region which must be protected by a CP + protected mode. On some targets this region must cover + the entire SMMU register space, on others there + is a separate aperture for CP to program context banks. + +Optional properties: +- qcom,retention : A boolean specifying if retention is supported on this target +- qcom,global_pt : A boolean specifying if global pagetable should be used. + When not set we use per process pagetables +- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target + for secure buffer allocation + +- List of sub nodes, one for each of the translation context banks supported. + The driver uses the names of these nodes to determine how they are used, + currently supported names are: + - gfx3d_user : Used for the 'normal' GPU address space. + - gfx3d_secure : Used for the content protection address space. + - gfx3d_secure_alt : Used for the content protection address space for alternative SID. + + Each sub node has the following required properties: + + - compatible : "qcom,smmu-kgsl-cb" + - iommus : Specifies the SID's used by this context bank, this needs to be + pair, kgsl_smmu is the string parsed by iommu + driver to match this context bank with the kgsl_smmu device + defined in iommu device tree. On targets where the msm iommu + driver is used rather than the arm smmu driver, this property + may be absent. + +Example: + +msm_iommu: qcom,kgsl-iommu@2ca0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x2ca0000 0x10000>; + qcom,protect = <0xa0000 0xc000>; + clocks = <&clock_mmss clk_gpu_ahb_clk>, + <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, + <&clock_mmss clk_mmss_mmagic_ahb_clk>, + <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>; + clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk"; + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,global_pt; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0>, + <&kgsl_smmu 1>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>; + }; + + gfx3d_secure_alt: gfx3d_secure_alt { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>; + }; +}; diff --git a/bindings/adreno-pwrlevels.txt b/bindings/adreno-pwrlevels.txt new file mode 100644 index 00000000..43175535 --- /dev/null +++ b/bindings/adreno-pwrlevels.txt @@ -0,0 +1,94 @@ +Qualcomm Technologies, Inc. GPU powerlevels + +Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins) +can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a +voltage, bus, bandwidth level, and a DVM value. + +- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets + +Properties: +- compatible: Must be qcom,gpu-pwrlevel-bins +- qcom,gpu-pwrlevels: Defines a set of powerlevels + +Properties: +- qcom,speed-bin: Speed bin identifier for the set - if present + must match the value read from the hardware + +- qcom,sku-codes: List of SKU versions specified by P-Code and + Feature Code that can support this set of + powerlevels. An entry of 0 in this list matches + any SKU and can be used as a fallback if other + powerlevel sets are not matched + +- qcom,initial-pwrlevel: GPU wakeup powerlevel +- qcom,initial-min-pwrlevel: Initial minimum available GPU powerlevel + +- qcom,gpu-pwrlevel: A single powerlevel + +- qcom,ca-target-pwrlevel: + This value indicates which qcom,gpu-pwrlevel + to jump on in case of context aware power level + jump. +Required Properties: +- reg: Index of the powerlevel (0 = highest perf) +- qcom,gpu-freq GPU frequency for the powerlevel (in Hz) +- qcom,bus-freq Index to a bus level (defined by the bus + settings). + +- qcom,bus-freq-ddrX If specified, define the DDR specific bus + frequency for the power level. X will be the + return value from of_fdt_get_ddrtype(). + +Optional Properties: +- qcom,bus-min Minimum bus level to set for the power level + +- qcom,bus-min-ddrX If specified, define the DDR specific minimum + bus level for the power level. X will be the + return value from of_fdt_get_ddrtype(). + +- qcom,bus-max maximum bus level to set for the power level + +- qcom,bus-max-ddrX If specified, define the DDR specific maximum + bus level for the power level. X will be the + return value from of_fdt_get_ddrtype(). + +- qcom,acd-level: Value that is used as a register setting for + the ACD power feature. It helps to determine + the threshold for when ACD activates. Zero is + the default value, and the setting where ACD + will never activate. + +- qcom,cx-level: Specifies the CX vote required for each GPU power + level. + +Example: + +qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + qcom,acd-level = <0xffffffff>; + qcom,cx-level = ; +}; + +Example for DDR4/DDR5 specific part: + +qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <480000000>; + qcom,cx-level = ; + + /* DDR5 */ + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <9>; + qcom,bus-max-ddr8 = <11>; + + /* DDR 4 */ + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <9>; + + qcom,acd-level = <0xffffffff>; +}; diff --git a/bindings/adreno.txt b/bindings/adreno.txt new file mode 100644 index 00000000..5c50499a --- /dev/null +++ b/bindings/adreno.txt @@ -0,0 +1,528 @@ +Qualcomm Technologies, Inc. GPU + +Qualcomm Technologies, Inc. Adreno GPU + +Required properties: +- compatible: Must be "qcom,kgsl-3d0". + May also includes "qcom,adreno-gpu-*" for few targets. + Must include "qcom,adreno-gpu-a619-holi" for Holi target. + Must include "qcom,adreno-gpu-a621" for Neo target. + Must include "qcom,adreno-gpu-a660-shima" for Shima target. + Must include "qcom,adreno-gpu-gen7-0-0" for Waipio target. + Must include "qcom,adreno-gpu-gen7-0-1" for Waipio V2 target. + Must include "qcom,adreno-gpu-gen7-2-0" for Kalama target. + Must include "qcom,adreno-gpu-gen7-2-1" for Kalama V2 target. + Must include "qcom,adreno-gpu-gen7-4-0" for Cape target. + Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target. + Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target. + Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target. +- reg: Specifies the list of register regions for the device. +- reg-names: Resource names used for the register regions specified + in reg. +- interrupts: Interrupt mapping for GPU nterrupts. +- interrupt-names: String property to describe the names of the interrupts. +- qcom,gpu-bimc-interface-clk-freq: + GPU-BIMC interface clock needs to set to this value for + targets where B/W requirements does not meet GPU Turbo + use cases. +- clocks: List of phandle and clock specifier pairs, one pair + for each clock input to the device. +- clock-names: List of clock input name strings sorted in the same + order as the clocks property. + +- qcom,base-leakage-coefficient: Dynamic leakage coefficient. +- qcom,lm-limit: Current limit for GPU limit management. +- qcom,isense-clk-on-level: below or equal this power level isense clock is at XO rate, + above this powerlevel isense clock is at working frequency. + +Bus Scaling Data: +- qcom,gpu-bus-table: Defines a bus voting table with the below properties. Multiple sets of bus + voting tables can be defined for given platform based on the type of ddr system. + +Properties: +- compatible: Must be "qcom,gpu-bus-table". Additionally, "qcom,gpu-bus-table-ddr" must also + be provided, with the ddr type value(integer) appended to the string. +- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor. +- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property. +- qcom,msm-bus,active-only: A boolean flag indicating if it is active only. +- qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase. +- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is: + , , // For Bus Scaling Usecase 1 + , , // For Bus Scaling Usecase 2 + <.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n + This property is a series of all vectors for all Bus Scaling Usecases. + Each set of vectors for each usecase describes bandwidth votes for a combination + of src/dst ports. The driver will set the desired use case based on the selected + power level and the desired bandwidth vote will be registered for the port pairs. + Current values of src are: + 0 = MSM_BUS_MASTER_GRAPHICS_3D + 1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1 + 2 = MSM_BUS_MASTER_V_OCMEM_GFX3D + Current values of dst are: + 0 = MSM_BUS_SLAVE_EBI_CH0 + 1 = MSM_BUS_SLAVE_OCMEM + ab: Represents aggregated bandwidth. This value is 0 for Graphics. + ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s> + +- qcom,ocmem-bus-client: Container for another set of bus scaling properties + qcom,msm-bus,name + qcom,msm-bus,num-cases + qcom,msm-bus,num-paths + qcom,msm-bus,vectors-KBps + to be used by ocmem msm bus scaling client. + +GDSC Oxili Regulators: +- regulator-names: List of regulator name strings sorted in power-on order +- vddcx-supply: Phandle for vddcx regulator device node. +- vdd-supply: Phandle for vdd regulator device node. + +IOMMU Data: +- iommu: Phandle for the KGSL IOMMU device node + +GPU Power levels: +- qcom,gpu-pwrlevel-bins: Container for sets of GPU power levels (see + adreno-pwrlevels.txt) +DCVS Core info +- qcom,dcvs-core-info Container for the DCVS core info (see + dcvs-core-info.txt) + +Optional Properties: +- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time + and when coming back out of resume +- qcom,throttle-pwrlevel: This value indicates which qcom,gpu-pwrlevel LM throttling + may start to occur +- qcom,bus-control: Boolean. Enables an independent bus vote from the gpu frequency +- qcom,bus-width: Bus width in number of bytes. This enables dynamic AB bus voting based on + bus width and actual bus transactions. +- qcom,bus-accesses: Parameter for tuning bus dcvs. +- qcom,bus-accesses-ddrX: Parameter for tuning bus dcvs for each DDR configuration where + X will be the return value from of_fdt_get_ddrtype(). +- qcom,gpubw-dev: a phandle to a device representing bus bandwidth requirements + (see devdw.txt) +- qcom,idle-timeout: This property represents the time in milliseconds for idle timeout. +- qcom,no-nap: If it exists software clockgating will be disabled at boot time. +- qcom,chipid: If it exists this property is used to replace + the chip identification read from the GPU hardware. + This is used to override faulty hardware readings. +- qcom,gpu-model: If it exists this property is used for GPU model name. +- qcom,vk-device-id: If it exists this property is used to specify vulkan device ID. +- qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event. +- qcom,disable-busy-time-burst: + Boolean. Disables the busy time burst to avoid switching + of power level for large frames based on the busy time limit. + +- qcom,pm-qos-active-latency: + Right after GPU wakes up from sleep, driver votes for + acceptable maximum latency to the pm-qos driver. This + voting demands that the system can not go into any + power save state *if* the latency to bring system back + into active state is more than this value. + Value is in microseconds. +- qcom,pm-qos-wakeup-latency: + Similar to the above. Driver votes against deep low + power modes right before GPU wakes up from sleep. +- qcom,l2pc-cpu-mask-latency: + The CPU mask latency in microseconds to avoid L2PC + on masked CPUs. + +- qcom,gpu-cx-ipeak: + CX Ipeak is a mitigation scheme which throttles cDSP frequency + if all the clients are running at their respective threshold + frequencies to limit CX peak current. + + phandle - phandle of CX Ipeak device node + bit - Every bit corresponds to a client of CX Ipeak + driver in the relevant register. +- qcom, gpu-cx-ipeak-freq: + GPU frequency threshold for CX Ipeak voting. GPU votes + to CX Ipeak driver when GPU clock crosses this threshold. + CX Ipeak can limit peak current based on voting from other clients. + +- qcom,force-32bit: + Force the GPU to use 32 bit data sizes even if + it is capable of doing 64 bit. + +- qcom,gpu-speed-bin: GPU speed bin information in the format + + offset - offset of the efuse register from the base. + mask - mask for the relevant bits in the efuse register. + shift - number of bits to right shift to get the speed bin + value. +- qcom,gpu-disable-fuse: GPU disable fuse + + offset - offset of the efuse register from the base. + mask - mask for the relevant bits in the efuse register. + shift - number of bits to right shift to get the disable_gpu + fuse bit value. + +- qcom,soc-hw-rev-efuse: SOC hardware revision fuse information in the format + + offset - offset of the efuse register from the base. + bit_position - hardware revision starting bit in the efuse register. + mask - mask for the relevant bits in the efuse register. + +- qcom,highest-bank-bit: + Specify the bit of the highest DDR bank. This + is programmed into protected registers and also + passed to the user as a property. +- qcom,min-access-length: + Specify the minimum access length for the chip. + Either 32 or 64 bytes. + Based on the above options, program the appropriate bit into + certain protected registers and also pass to the user as + a property. +- qcom,ubwc-mode: + Specify the ubwc mode for this chip. + 1: UBWC 1.0 + 2: UBWC 2.0 + 3: UBWC 3.0 + Based on the ubwc mode, program the appropriate bit into + certain protected registers and also pass to the user as + a property. +- qcom,l2pc-cpu-mask: + Disables L2PC on masked CPUto the string.rendering thread is running on masked CPUs. + Bit 0 is for CPU-0, bit 1 is for CPU-1... + +- qcom,l2pc-update-queue: + Disables L2PC on masked CPUs at queue time when it's true. + +- qcom,snapshot-size: + Specify the size of snapshot in bytes. This will override + snapshot size defined in the driver code. + +- qcom,enable-ca-jump: + Boolean. Enables use of context aware DCVS +- qcom,ca-busy-penalty: + This property represents the time in microseconds required to + initiate context aware power level jump. +- qcom,ca-target-pwrlevel: + This value indicates which qcom,gpu-pwrlevel to jump on in case + of context aware power level jump. + +- qcom,gpu-qdss-stm: + + baseAddr - base address of the gpu channels in the qdss stm memory region + size - size of the gpu stm region + +- qcom,gpu-timer: + + baseAddr - base address of the qtimer memory region + size - size of the qtimer region + +- qcom,tzone-names: + Specify the names of GPU thermal zones. These will be used + to get gpu temperature from the thermal driver API. + + nvmem-cells: + A phandle to the configuration data such as gpu speed bin, gpu gaming mode, + gpu model name provided by a nvmem device. If unspecified default values shall be used. + nvmem-cell-names: + Should be "speed_bin", "gaming_bin", "gpu_model" + +GPU Quirks: +- qcom,gpu-quirk-two-pass-use-wfi: + Signal the GPU to set Set TWOPASSUSEWFI bit in + PC_DBG_ECO_CNTL (5XX and 6XX only) +- qcom,gpu-quirk-critical-packets: + Submit a set of critical PM4 packets when the GPU wakes up +- qcom,gpu-quirk-fault-detect-mask: + Mask out RB1-3 activity signals from HW hang + detection logic +- qcom,gpu-quirk-dp2clockgating-disable: + Disable RB sampler data path clock gating optimization +- qcom,gpu-quirk-lmloadkill-disable: + Use register setting to disable local memory(LM) feature + to avoid corner case error +- qcom,gpu-quirk-hfi-use-reg: + Use registers to replace DCVS HFI message to avoid GMU failure + to access system memory during IFPC +- qcom,gpu-quirk-limit-uche-gbif-rw: + Limit number of read and write transactions from UCHE block to + GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC. +- qcom,gpu-quirk-mmu-secure-cb-alt: + Select alternate secure context bank to generate SID1 for + secure playback. + +KGSL Memory Pools: +- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets + (pools) can be defined within qcom,gpu-mempools. + Each mempool defines a pool order, reserved pages, + allocation allowed. +Properties: +- compatible: Must be qcom,gpu-mempools. +- qcom,mempool-max-pages: Max pages for all mempools, If not defined there is no limit. +- qcom,gpu-mempool: Defines a set of mempools. + +Properties: +- reg: Index of the pool (0 = lowest pool order). +- qcom,mempool-page-size: Size of page. +- qcom,mempool-reserved: Number of pages reserved at init time for a pool. +- qcom,mempool-allocate: Allocate memory from the system memory when the + reserved pool exhausted. +- qcom,mempool-max-pages: Limit on max pages this pool can hold, If not defined + there is no limit. +GPU model configuration: +- qcom,gpu-models: + Container of sets of GPU model names specified by qcom,gpu-models. +Properties: +- compatible: + Must be qcom,gpu-models. + +- qcom,gpu-model: + Defines a GPU model name for specific GPU model ID. + +Properties: +- compatible: + May also include "qcom,adreno-gpu-*" for few targets. +- qcom,gpu-model-id: + Identifier for the specific GPU hardware configuration - must match the value read + from the hardware. +- qcom,gpu-model: + GPU model name for a specific GPU hardware. + +- qcom,vk-device-id: + Vulkan device id unique for specific GPU hardware model. +SOC Hardware revisions: +- qcom,soc-hw-revisions: + Container of sets of SOC hardware revisions specified by + qcom,soc-hw-revision. +Properties: +- compatible: + Must be qcom,soc-hw-revisions. + +- qcom,soc-hw-revision: + Defines a SOC hardware revision. + +Properties: +- qcom,soc-hw-revision: + Identifier for the hardware revision - must match the value read + from the hardware. +- qcom,chipid: + GPU Chip ID to be used for this hardware revision. +- qcom,gpu-quirk-*: + GPU quirks applicable for this hardware revision. + +GPU LLC slice info: +- cache-slice-names: List of LLC cache slices for GPU transactions + and pagetable walk. +- cache-slices: phandle to the system LLC driver, cache slice index. + +L3 Power levels: +- qcom,l3-pwrlevels: Container for sets of L3 power levels, the + L3 frequency is adjusted according to the + performance hint received from userspace. + +Properties: +- compatible: Must be qcom,l3-pwrlevels +- qcom,l3-pwrlevel: A single L3 powerlevel + +Properties: +- reg: Index of the L3 powerlevel + 0 = powerlevel for no L3 vote + 1 = powerlevel for medium L3 vote + 2 = powerlevel for maximum L3 vote +- qcom,l3-freq: The L3 frequency for the powerlevel (in Hz) + +GPU coresight info: +The following properties are optional as collecting data via coresight might +not be supported for every chipset. The documentation for coresight +properties can be found in: +Documentation/devicetree/bindings/coresight/coresight.txt + +- qcom,gpu-coresights: Container for sets of GPU coresight sources. +- coresight-id: Unique integer identifier for the bus. +- coresight-name: Unique descriptive name of the bus. +- coresight-nr-inports: Number of input ports on the bus. +- coresight-outports: List of output port numbers on the bus. +- coresight-child-list: List of phandles pointing to the children of this + component. +- coresight-child-ports: List of input port numbers of the children. +- coresight-atid: The unique ATID value of the coresight device + +Example of A330 GPU in MSM8916: + +&soc { + msm_gpu: qcom,kgsl-3d0@1c00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0x1c00000 0x10000 + 0x1c20000 0x20000>; + reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000600>; + + qcom,initial-pwrlevel = <1>; + + /* Idle Timeout = HZ/12 */ + qcom,idle-timeout = <8>; + qcom,strtstp-sleepwake; + + clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>, + <&clock_gcc clk_gcc_oxili_ahb_clk>, + <&clock_gcc clk_gcc_oxili_gmem_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_bimc_gpu_clk>; + clock-names = "core_clk", "iface_clk", "mem_clk", + "mem_iface_clk", "alt_mem_iface_clk"; + + /* Bus Scale Settings */ + qcom, gpu-bus-table { + compatible="qcom,gpu-bus-table","qcom,gpu-bus-table-ddr7"; + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 1600000>, + <26 512 0 3200000>, + <26 512 0 4264000>; + }; + + /* GDSC oxili regulators */ + vdd-supply = <&gdsc_oxili_gx>; + + nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>; + nvmem-cell-names = "speed_bin", "gaming_bin","gpu_model"; + + /* IOMMU Data */ + iommu = <&gfx_iommu>; + + /* Trace bus */ + coresight-id = <67>; + coresight-name = "coresight-gfx"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <5>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <1>; + + qcom,soc-hw-revisions { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,soc-hw-revisions"; + + qcom,soc-hw-revision@0 { + reg = <0>; + + qcom,chipid = <0x06010500>; + qcom,gpu-quirk-hfi-use-reg; + qcom,gpu-quirk-limit-uche-gbif-rw; + }; + + qcom,soc-hw-revision@1 { + reg = <1>; + + qcom,chipid = <0x06010501>; + qcom,gpu-quirk-hfi-use-reg; + }; + }; + + qcom,gpu-models { + #address-cells = <1>; + #size-cells = <0>; + compatible="qcom,gpu-models"; + + qcom,gpu-model@0 { + compatible="qcom,adreno-gpu-a642l"; + qcom,gpu-model-id = <0>; + qcom,gpu-model = "Adreno642Lv1"; + qcom,vk-device-id= <0x06030500>; + }; + qcom,gpu-model@1 { + compatible="qcom,adreno-gpu-a645"; + qcom,gpu-model-id = <190>; + qcom,gpu-model = "Adreno645"; + qcom,vk-device-id= <0x06030500>; + }; + } + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels-bins { + #address-cells = <1>; + #size-cells = <0>; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,ca-target-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <310000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <66>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + }; + + }; +}; diff --git a/gpu/pineapple-gpu-pwrlevels.dtsi b/gpu/pineapple-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..f4ac7ed4 --- /dev/null +++ b/gpu/pineapple-gpu-pwrlevels.dtsi @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L1 0x882f5ffd +#define ACD_LEVEL_TURBO 0x882f5ffd +#define ACD_LEVEL_NOM_L1 0x882f5ffd +#define ACD_LEVEL_NOM 0xc0285ffd +#define ACD_LEVEL_SVS_L2 0xe0295ffd +#define ACD_LEVEL_SVS_L1 0xe0295ffd +#define ACD_LEVEL_SVS_L0 0xc02a5ffd +#define ACD_LEVEL_SVS 0xc02a5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS 0xc02f5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd + +&msm_gpu { + /* Power levels */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,sku-codes = ; + qcom,speed-bin = <2>; + + qcom,initial-pwrlevel = <12>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <903000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <869000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <8>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <834000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <720000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <680000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <629000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <578000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <422000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <366000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <231000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,sku-codes = ; + + qcom,initial-pwrlevel = <11>; + + /* Turbo */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <869000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <834000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <720000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <680000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <629000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <578000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <2>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <422000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <366000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <231000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,sku-codes = ; + + qcom,initial-pwrlevel = <12>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <903000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <869000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <8>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <834000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <720000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <680000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <629000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <578000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <2>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <422000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <366000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <231000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,sku-codes = ; + + qcom,initial-pwrlevel = <10>; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <834000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <720000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <680000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <629000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <578000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <2>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <422000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <366000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <231000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; + }; +}; diff --git a/gpu/pineapple-gpu.dts b/gpu/pineapple-gpu.dts new file mode 100644 index 00000000..0efcc076 --- /dev/null +++ b/gpu/pineapple-gpu.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pineapple-gpu.dtsi" +#include "pineapple-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <577 0x10000>; + qcom,board-id = <0 0>; +}; + diff --git a/gpu/pineapple-gpu.dtsi b/gpu/pineapple-gpu.dtsi new file mode 100644 index 00000000..4bcd66e8 --- /dev/null +++ b/gpu/pineapple-gpu.dtsi @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +/* External feature codes */ +#define FC_UNKNOWN 0x0 +#define FC_AA 0x1 +#define FC_AB 0x2 +#define FC_AC 0x3 +#define FC_AD 0x4 + +/* Internal feature codes */ +#define FC_Y0 0x00f1 +#define FC_Y1 0x00f2 + +/* Pcodes */ +#define PCODE_UNKNOWN 0 +#define PCODE_0 1 +#define PCODE_1 2 +#define PCODE_2 3 +#define PCODE_3 4 +#define PCODE_4 5 +#define PCODE_5 6 +#define PCODE_6 7 +#define PCODE_7 8 + +#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen7-9-0", "qcom,kgsl-3d0"; + status = "ok"; + reg = <0x3d00000 0x40000>, <0x3d61000 0x3000>, + <0x03d50000 0x10000>, <0x03d9e000 0x2000>, + <0x10900000 0x80000>, <0x10048000 0x8000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc", + "qdss_gfx", "qdss_etr", "qdss_tmc"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&aoss_qmp QDSS_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "apb_pclk"; + + qcom,gpu-model = "Adreno750"; + + qcom,chipid = <0x43051400>; + + qcom,no-nap; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <4>; + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + + qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", + "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + ; /* index=9 */ + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x03da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d69000 { + compatible = "qcom,gen7-gmu"; + + reg = <0x3d68000 0x37000>, + <0xb280000 0x10000>, + <0x03D40000 0x10000>; + + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gpu_cc_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk"; + + qcom,gmu-freq-table = <260000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <625000000 RPMH_REGULATOR_LEVEL_SVS>; + qcom,gmu-perf-ddr-bw = ; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + + qcom,ipc-core = <0x00400000 0x140000>; + + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + + coresight_cx_dgbc: qcom,gpu-coresight-cx { + compatible = "qcom,gpu-coresight-cx"; + + coresight-name = "coresight-gfx-cx"; + coresight-atid = <52>; + + out-ports { + port { + cx_dbgc_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_cx_dbgc>; + }; + }; + }; + }; + + coresight_gx_dgbc: qcom,gpu-coresight-gx { + compatible = "qcom,gpu-coresight-gx"; + + coresight-name = "coresight-gfx"; + coresight-atid = <53>; + + out-ports { + port { + gx_dbgc_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_gx_dbgc>; + }; + }; + }; + }; +}; + +&funnel_gfx { + status = "ok"; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_in_gx_dbgc: endpoint { + remote-endpoint = + <&gx_dbgc_out_funnel_gfx>; + }; + }; + + port@1 { + reg = <1>; + funnel_gfx_in_cx_dbgc: endpoint { + remote-endpoint = + <&cx_dbgc_out_funnel_gfx>; + }; + }; + }; +}; diff --git a/gpu/pineapple-v2-gpu-pwrlevels.dtsi b/gpu/pineapple-v2-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..55632018 --- /dev/null +++ b/gpu/pineapple-v2-gpu-pwrlevels.dtsi @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L1 0x882f5ffd +#define ACD_LEVEL_TURBO 0x882f5ffd +#define ACD_LEVEL_NOM_L1 0x882f5ffd +#define ACD_LEVEL_NOM 0xc0285ffd +#define ACD_LEVEL_SVS_L2 0xe0295ffd +#define ACD_LEVEL_SVS_L1 0xe0295ffd +#define ACD_LEVEL_SVS_L0 0xc02a5ffd +#define ACD_LEVEL_SVS 0xc02a5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS 0xc02f5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd + +&msm_gpu { + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,initial-pwrlevel = <11>; + + /* Turbo */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <903000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <834000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* Nom */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <770000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <720000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <680000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <629000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <578000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <422000000>; + qcom,level = ; + + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <366000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <5>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <231000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; +}; diff --git a/gpu/pineapple-v2-gpu.dts b/gpu/pineapple-v2-gpu.dts new file mode 100644 index 00000000..5417d43c --- /dev/null +++ b/gpu/pineapple-v2-gpu.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pineapple-v2-gpu.dtsi" +#include "pineapple-v2-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x20000>, <577 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/pineapple-v2-gpu.dtsi b/gpu/pineapple-v2-gpu.dtsi new file mode 100644 index 00000000..5a110782 --- /dev/null +++ b/gpu/pineapple-v2-gpu.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-gpu.dtsi" + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0"; + + qcom,gpu-model = "Adreno750v2"; + + qcom,chipid = <0x43051401>; +}; From 713410db8fcc1b2808c5f65e8af618e2a8e8ea43 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Wed, 16 Aug 2023 16:31:57 -0700 Subject: [PATCH 003/113] ARM: dts: msm: Add support for Sun GPU Add the devicetree files for the GPU on Sun devices. Change-Id: Iaf7a19eb5e2c6c215e838ae1bfa3b01916c804d9 Signed-off-by: Hareesh Gundu --- Kbuild | 4 + gpu/sun-gpu-pwrlevels.dtsi | 132 +++++++++++++++++++++++++++ gpu/sun-gpu.dts | 26 ++++++ gpu/sun-gpu.dtsi | 177 +++++++++++++++++++++++++++++++++++++ 4 files changed, 339 insertions(+) create mode 100644 gpu/sun-gpu-pwrlevels.dtsi create mode 100644 gpu/sun-gpu.dts create mode 100644 gpu/sun-gpu.dtsi diff --git a/Kbuild b/Kbuild index 2ef6de5a..82161dd3 100644 --- a/Kbuild +++ b/Kbuild @@ -3,6 +3,10 @@ dtbo-y += gpu/pineapple-gpu.dtbo \ gpu/pineapple-v2-gpu.dtbo endif +ifeq ($(CONFIG_ARCH_SUN), y) +dtbo-y += gpu/sun-gpu.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..3699a791 --- /dev/null +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&msm_gpu { + /* Power levels */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <9>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <930000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <779000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + }; +}; diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts new file mode 100644 index 00000000..98f76718 --- /dev/null +++ b/gpu/sun-gpu.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sun-gpu.dtsi" +#include "sun-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sun"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi new file mode 100644 index 00000000..591962f5 --- /dev/null +++ b/gpu/sun-gpu.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +/* External feature codes */ +#define FC_UNKNOWN 0x0 + +/* Pcodes */ +#define PCODE_UNKNOWN 0 + +#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen8-0-0", "qcom,kgsl-3d0"; + status = "disabled"; + reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, + <0x3d61000 0x3000>, <0x3d9e000 0x2000>, + <0x10900000 0x80000>, <0x10048000 0x8000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", + "qdss_gfx", "qdss_etr", "qdss_tmc"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gpu_cc_ahb"; + + qcom,gpu-model = "Adreno830"; + + qcom,chipid = <0x44050000>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <5>; + + qcom,gpu-qdss-stm = <0x37000000 0x40000>; /* base addr, size */ + + qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", + "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* NOM index=8 */ + , /* TURBO index=9 */ + , /* TURBO_L1 index=10 */ + ; /* TURBO_L3 index=11 */ + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x3da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d37000 { + compatible = "qcom,gen8-gmu"; + + reg = <0x3d37000 0x68000>, + <0xb5d0000 0x24000>, + <0x3d40000 0x10000>; + + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gx_clkctl_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk"; + + qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <650000000 RPMH_REGULATOR_LEVEL_SVS>; + qcom,gmu-perf-ddr-bw = ; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + }; +}; From 325eb7a0280ab7a2d88dec9acc5a185687ed87e3 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Mon, 16 Oct 2023 09:39:18 -0700 Subject: [PATCH 004/113] adreno: dts: Enable graphics rendering for Sun Enable Sun GPU to perform graphics functionality. Also add ipc-core property for hwfences support. Change-Id: Ia01d92e4b2d43a1f8ec24ff63768aab5d7a4e1e3 Signed-off-by: Hareesh Gundu --- gpu/sun-gpu.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 591962f5..fc9a79af 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -15,7 +15,7 @@ &msm_gpu { compatible = "qcom,adreno-gpu-gen8-0-0", "qcom,kgsl-3d0"; - status = "disabled"; + status = "ok"; reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, <0x3d61000 0x3000>, <0x3d9e000 0x2000>, <0x10900000 0x80000>, <0x10048000 0x8000>, @@ -173,5 +173,7 @@ iommus = <&kgsl_smmu 0x5 0x000>; qcom,iommu-dma = "disabled"; + + qcom,ipc-core = <0x00400000 0x140000>; }; }; From cffcc8cffb6c415e559f262221d394f68c6971a4 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Mon, 20 Nov 2023 09:34:44 -0800 Subject: [PATCH 005/113] ARM: dts: msm: Update supported frequencies for Sun GPU Add intermediate supported power levels for GPU and remove unsupported power levels from the list. Change-Id: Ie16c06293dc707561f03aa9f1839a8217f163726 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 70 +++++++++++++++++++++++++------------- 1 file changed, 46 insertions(+), 24 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 3699a791..77be73e5 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -15,7 +15,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; /* TURBO_L1 */ @@ -29,20 +29,9 @@ qcom,bus-max = <11>; }; - /* TURBO */ + /* NOM_L1 */ qcom,gpu-pwrlevel@1 { reg = <1>; - qcom,gpu-freq = <930000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <10>; - qcom,bus-max = <11>; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -52,8 +41,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -63,8 +52,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <779000000>; qcom,level = ; @@ -74,8 +63,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -84,6 +73,17 @@ qcom,bus-max = <10>; }; + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + /* SVS */ qcom,gpu-pwrlevel@6 { reg = <6>; @@ -95,9 +95,20 @@ qcom,bus-max = <7>; }; - /* Low_SVS */ + /* Low_SVS_L1 */ qcom,gpu-pwrlevel@7 { reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -106,9 +117,20 @@ qcom,bus-max = <6>; }; + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -118,8 +140,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <222000000>; qcom,level = ; From 17f495d10fc5d4e7e9a3037904055f2447ca4691 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Mon, 20 Nov 2023 10:22:48 -0800 Subject: [PATCH 006/113] ARM: dts: msm: Add QDSS clock to sun GPU QDSS clock is used in kgsl to program ISDB registers. Add the clock so that kgsl can vote for it when needed. Change-Id: I2b71bdc4b9884409c598ba20759c56bff12cdb64 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index fc9a79af..46db9ce5 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -27,9 +27,11 @@ interrupt-names = "kgsl_3d0_irq"; clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>; + <&gpucc GPU_CC_AHB_CLK>, + <&aoss_qmp QDSS_CLK>; clock-names = "gcc_gpu_memnoc_gfx", - "gpu_cc_ahb"; + "gpu_cc_ahb", + "apb_pclk"; qcom,gpu-model = "Adreno830"; From 8687f5ac09353094e49a667305dad9476e260a98 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Wed, 2 Aug 2023 08:17:33 +0530 Subject: [PATCH 007/113] dt-bindings: Add property to specify gpu power domains GDSCs can be modeled as power domain on newer GPUs. This property provides an option to specify the GDSCs as power domain. Change-Id: I2f687b9339accaad701737ccfaf5e41209201229 Signed-off-by: Kamal Agrawal --- bindings/adreno.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/adreno.txt b/bindings/adreno.txt index 5c50499a..dd426a95 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -76,6 +76,13 @@ GDSC Oxili Regulators: - vddcx-supply: Phandle for vddcx regulator device node. - vdd-supply: Phandle for vdd regulator device node. +Power Domains: +- power-domains: List of PM domain specifiers that reference each power-domain + used by the GPU +- power-domain-names: List of names that represent each of the specifiers in the + 'power-domains' property. Includes 'gpu_cx' and 'gpu_gx' which + represent the power-domains for CX and GX GDSC, respectively. + IOMMU Data: - iommu: Phandle for the KGSL IOMMU device node From 87ec4506c6e933834918d21aee907b696c2a6653 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Mon, 18 Dec 2023 10:05:57 -0700 Subject: [PATCH 008/113] ARM: dts: msm: Add sunp msm-id support for GPU Add support for sunp variant msm-id. Change-Id: I3dee70f03e360330636290ef665aced0b4f31542 Signed-off-by: Carter Cooper Signed-off-by: Hareesh Gundu --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index 98f76718..eda85863 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>; + qcom,msm-id = <618 0x10000>, <639 0x10000>; qcom,board-id = <0 0>; }; From 0d12082da370c5a504bc76ffbbbfeabcc1d7a221 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Fri, 15 Dec 2023 12:57:16 +0530 Subject: [PATCH 009/113] ARM: dts: msm: Remove gmu_pdc register for sun GPU KGSL driver doesn't program PDC registers anymore. Thus, remove the register information from device tree for sun GPU. Change-Id: I60c78e00942bb68e311b4c4632e5a3e2ed30dcd6 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..9672d772 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -145,10 +145,9 @@ compatible = "qcom,gen8-gmu"; reg = <0x3d37000 0x68000>, - <0xb5d0000 0x24000>, <0x3d40000 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + reg-names = "gmu", "gmu_ao_blk_dec0"; interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, <0 305 IRQ_TYPE_LEVEL_HIGH>; From 791bff1a21ca7cbb7e2dbfb874dac70ea6dcc843 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Sat, 20 Jan 2024 14:59:59 +0530 Subject: [PATCH 010/113] ARM: dts: msm: Add coresight configurations for sun Add device tree nodes for coresight CX and GX DBGC blocks for sun devices. Also, add coresight funnel configuration for graphics funnel device. Change-Id: Id0a73ac9ef51e1039b718d5d51a4fc063d218a94 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..36642261 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -178,4 +178,58 @@ qcom,ipc-core = <0x00400000 0x140000>; }; + + coresight_cx_dgbc: qcom,gpu-coresight-cx { + compatible = "qcom,gpu-coresight-cx"; + + coresight-name = "coresight-gfx-cx"; + + out-ports { + port { + cx_dbgc_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_cx_dbgc>; + }; + }; + }; + }; + + coresight_gx_dgbc: qcom,gpu-coresight-gx { + compatible = "qcom,gpu-coresight-gx"; + + coresight-name = "coresight-gfx"; + + out-ports { + port { + gx_dbgc_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_gx_dbgc>; + }; + }; + }; + }; +}; + +&funnel_gfx { + status = "ok"; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_in_gx_dbgc: endpoint { + remote-endpoint = + <&gx_dbgc_out_funnel_gfx>; + }; + }; + + port@1 { + reg = <1>; + funnel_gfx_in_cx_dbgc: endpoint { + remote-endpoint = + <&cx_dbgc_out_funnel_gfx>; + }; + }; + }; }; From 88a17ffa07b25e06184a0011b4b41fac4b7a070f Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 5 Jan 2024 15:58:06 -0700 Subject: [PATCH 011/113] dt-bindings: Add soccp controller property This is needed to vote for soccp boot/slumber sequence for hardware fence feature. Change-Id: I169d83ed9d5acf66027194bf5fee0825bb5602d2 Signed-off-by: Harshdeep Dhatt --- bindings/adreno-gmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/adreno-gmu.txt b/bindings/adreno-gmu.txt index a5544793..08173ede 100644 --- a/bindings/adreno-gmu.txt +++ b/bindings/adreno-gmu.txt @@ -66,6 +66,7 @@ GMU GDSC/regulators: baseAddr - base address of the IPC region size - size of the IPC region +- qcom,soccp-controller: Phandle of the soccp controller Example: From 65f3e20c5fc25d88740f398962aaa322dd5ee725 Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 5 Jan 2024 15:59:46 -0700 Subject: [PATCH 012/113] ARM: dts: msm: Add soccp controller phandle for sun Hardware fence feature requires that we keep soccp from power collapsing as long as GMU is active. Change-Id: I3721aefd8cb34edfeba846115132002defa8f385 Signed-off-by: Harshdeep Dhatt --- gpu/sun-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..4d34e4e4 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -177,5 +177,6 @@ qcom,iommu-dma = "disabled"; qcom,ipc-core = <0x00400000 0x140000>; + qcom,soccp-controller = <&soccp_pas>; }; }; From f535a812cb347c800d19c579c4167ff95e017a2b Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Mon, 11 Dec 2023 23:48:09 +0530 Subject: [PATCH 013/113] ARM: dts: msm: Add CX host interrupt for sun GPU For gen8 targets, frequency limiter violations are published through cx_host_irq interrupt. Thus, add cx_host_irq for sun GPU. Change-Id: Ie7e0c7fc53bdc002261ee05339c3e4c49da83ea0 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..04c9ab4c 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -23,8 +23,8 @@ reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq", "cx_host_irq"; clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, From 40c568a6d182095de26452c239be8bf3b0c88aea Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Sat, 3 Feb 2024 16:22:37 +0530 Subject: [PATCH 014/113] ARM: dts: msm: Update DDR bandwidth for sun GMU scaling SVS is the highest voltage corner for GMU. The lowest DDR BW that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX at a corner high enough such that GMU can run at 650 MHz. This is to get better GMU performance at no extra power cost. Change-Id: I919476577e9b2e69161142c93d47e91505ffc222 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..9d7d3cb1 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -171,7 +171,7 @@ qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, <650000000 RPMH_REGULATOR_LEVEL_SVS>; - qcom,gmu-perf-ddr-bw = ; + qcom,gmu-perf-ddr-bw = ; iommus = <&kgsl_smmu 0x5 0x000>; qcom,iommu-dma = "disabled"; From a17c326b0edba92fa3690da7ef45a13e1b7cfe5b Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Fri, 19 Jan 2024 16:03:19 -0800 Subject: [PATCH 015/113] ARM: dts: msm: Add powerlevels for AB and AC sku for sun gpu Add supporting power levels for AB and AC sku devices. Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 132 ++++++++++++++++++++++++++++++++++++- gpu/sun-gpu.dtsi | 18 ++++- 2 files changed, 148 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 77be73e5..9592390c 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ &msm_gpu { @@ -15,6 +15,136 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <10>; + qcom,sku-codes = ; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <779000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..a1a75788 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,15 +1,31 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) /* External feature codes */ #define FC_UNKNOWN 0x0 +#define FC_AA 0x1 +#define FC_AB 0x2 +#define FC_AC 0x3 +#define FC_AD 0x4 + +/* Internal feature codes */ +#define FC_Y0 0x00f1 +#define FC_Y1 0x00f2 /* Pcodes */ #define PCODE_UNKNOWN 0 +#define PCODE_0 1 +#define PCODE_1 2 +#define PCODE_2 3 +#define PCODE_3 4 +#define PCODE_4 5 +#define PCODE_5 6 +#define PCODE_6 7 +#define PCODE_7 8 #define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) From 01aa8e54306ef2de77d1deea4bc48d7bb3adc980 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Mon, 18 Dec 2023 10:05:57 -0700 Subject: [PATCH 016/113] ARM: dts: msm: Add sunp msm-id support for GPU Add support for sunp variant msm-id. Change-Id: I3dee70f03e360330636290ef665aced0b4f31542 Signed-off-by: Carter Cooper Signed-off-by: Hareesh Gundu Signed-off-by: Vaishali Gupta --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index 98f76718..eda85863 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>; + qcom,msm-id = <618 0x10000>, <639 0x10000>; qcom,board-id = <0 0>; }; From 4912910ea10cae8c21f36caaee58ad4e427e84c8 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Fri, 19 Jan 2024 16:03:19 -0800 Subject: [PATCH 017/113] ARM: dts: msm: Add powerlevels for AB and AC sku for sun gpu Add supporting power levels for AB and AC sku devices. Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d Signed-off-by: Mohammed Mirza Mandayappurath Manzoor Signed-off-by: Vaishali Gupta --- gpu/sun-gpu-pwrlevels.dtsi | 132 ++++++++++++++++++++++++++++++++++++- gpu/sun-gpu.dtsi | 18 ++++- 2 files changed, 148 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 77be73e5..9592390c 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ &msm_gpu { @@ -15,6 +15,136 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <10>; + qcom,sku-codes = ; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <779000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..a1a75788 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,15 +1,31 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) /* External feature codes */ #define FC_UNKNOWN 0x0 +#define FC_AA 0x1 +#define FC_AB 0x2 +#define FC_AC 0x3 +#define FC_AD 0x4 + +/* Internal feature codes */ +#define FC_Y0 0x00f1 +#define FC_Y1 0x00f2 /* Pcodes */ #define PCODE_UNKNOWN 0 +#define PCODE_0 1 +#define PCODE_1 2 +#define PCODE_2 3 +#define PCODE_3 4 +#define PCODE_4 5 +#define PCODE_5 6 +#define PCODE_6 7 +#define PCODE_7 8 #define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) From b884d6ef26f910f6cfe113e4e094018823d04337 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Fri, 15 Dec 2023 09:57:30 -0700 Subject: [PATCH 018/113] ARM: dts: msm: Add Sun GPU ACD values Add ACD values for supported voltage levels for Sun GPU. Change-Id: I8361f4026afbf05ba26860307ffc7158b55b8d2f Signed-off-by: Carter Cooper Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 60 ++++++++++++++++++++++++++++++++++++++ gpu/sun-gpu.dtsi | 2 ++ 2 files changed, 62 insertions(+) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 9592390c..86732352 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -3,6 +3,20 @@ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L1 0xa8285ffd +#define ACD_LEVEL_NOM_L1 0x88295ffd +#define ACD_LEVEL_NOM 0x88295ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0x882a5ffd +#define ACD_LEVEL_SVS_L0 0xa82b5ffd +#define ACD_LEVEL_SVS 0xa82c5ffd +#define ACD_LEVEL_LOW_SVS_L1 0x882e5ffd +#define ACD_LEVEL_LOW_SVS 0xc0295ffd +#define ACD_LEVEL_LOW_SVS_D0 0xc02a5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc02b5ffd +#define ACD_LEVEL_LOW_SVS_D2 0xe8285ffd + &msm_gpu { /* Power levels */ qcom,gpu-pwrlevel-bins { @@ -28,6 +42,8 @@ qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* NOM */ @@ -39,6 +55,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <7>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -50,6 +68,8 @@ qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -61,6 +81,8 @@ qcom,bus-freq = <8>; qcom,bus-min = <6>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* SVS_L0 */ @@ -72,6 +94,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -83,6 +107,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* Low_SVS_L1 */ @@ -94,6 +120,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -105,6 +133,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS_D0 */ @@ -116,6 +146,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -127,6 +159,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -138,6 +172,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -157,6 +193,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <10>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* NOM_L1 */ @@ -168,6 +206,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <7>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* NOM */ @@ -179,6 +219,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <7>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -190,6 +232,8 @@ qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -201,6 +245,8 @@ qcom,bus-freq = <8>; qcom,bus-min = <6>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* SVS_L0 */ @@ -212,6 +258,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -223,6 +271,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* Low_SVS_L1 */ @@ -234,6 +284,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -245,6 +297,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS_D0 */ @@ -256,6 +310,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -267,6 +323,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -278,6 +336,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; }; diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 858e0ad1..548a1bb0 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -193,5 +193,7 @@ qcom,ipc-core = <0x00400000 0x140000>; qcom,soccp-controller = <&soccp_pas>; + + qcom,qmp = <&aoss_qmp>; }; }; From 7222d36a739d9c0be546bc962c1b8de0b21f5a23 Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Sun, 17 Mar 2024 23:58:56 -0700 Subject: [PATCH 019/113] Revert "ARM: dts: msm: Add powerlevels for AB and AC sku for sun gpu" This reverts commit 4912910ea10cae8c21f36caaee58ad4e427e84c8. Signed-off-by: Vaishali Gupta Change-Id: I2684e486212a6d83d00f3942e6f1507fc0955ba7 --- gpu/sun-gpu-pwrlevels.dtsi | 132 +------------------------------------ gpu/sun-gpu.dtsi | 18 +---- 2 files changed, 2 insertions(+), 148 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 9592390c..77be73e5 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ &msm_gpu { @@ -15,136 +15,6 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <10>; - qcom,sku-codes = ; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - }; - - /* NOM */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <779000000>; - qcom,level = ; - - qcom,bus-freq = <9>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; - - /* SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - - qcom,gpu-pwrlevels-1 { - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index a1a75788..46db9ce5 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,31 +1,15 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) /* External feature codes */ #define FC_UNKNOWN 0x0 -#define FC_AA 0x1 -#define FC_AB 0x2 -#define FC_AC 0x3 -#define FC_AD 0x4 - -/* Internal feature codes */ -#define FC_Y0 0x00f1 -#define FC_Y1 0x00f2 /* Pcodes */ #define PCODE_UNKNOWN 0 -#define PCODE_0 1 -#define PCODE_1 2 -#define PCODE_2 3 -#define PCODE_3 4 -#define PCODE_4 5 -#define PCODE_5 6 -#define PCODE_6 7 -#define PCODE_7 8 #define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) From ae5cfaa4f59824448262fe3f3f127519ef212701 Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Sun, 17 Mar 2024 23:59:02 -0700 Subject: [PATCH 020/113] Revert "ARM: dts: msm: Add sunp msm-id support for GPU" This reverts commit 01aa8e54306ef2de77d1deea4bc48d7bb3adc980. Signed-off-by: Vaishali Gupta Change-Id: Ibc26bbfb334e389d871d5708d2dc1d86b26477e0 --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index eda85863..98f76718 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,msm-id = <618 0x10000>; qcom,board-id = <0 0>; }; From 300aef810b6a30b3912a02ab9d7c817ae03db6e5 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Tue, 5 Mar 2024 10:18:50 -0800 Subject: [PATCH 021/113] ARM: dts: msm: Add turbo_l3 power level to Sun GPU Add supported higher power level to Sun GPU. Change-Id: I6b33a69d09285f480bc24acfdd0df462ff25bcfb Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 62 +++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 24 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 86732352..5f15d4bd 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -4,6 +4,7 @@ */ /* ACD Control register values */ +#define ACD_LEVEL_TURBO_L3 0xa02f5ffd #define ACD_LEVEL_TURBO_L1 0xa8285ffd #define ACD_LEVEL_NOM_L1 0x88295ffd #define ACD_LEVEL_NOM 0x88295ffd @@ -181,12 +182,25 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,sku-codes = ; - /* TURBO_L1 */ + /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -198,8 +212,8 @@ }; /* NOM_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -211,8 +225,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -224,8 +238,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <779000000>; qcom,level = ; @@ -237,8 +251,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -250,8 +264,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -263,8 +277,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -276,8 +290,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -289,8 +303,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -302,8 +316,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -315,8 +329,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -328,8 +342,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <222000000>; qcom,level = ; From 2cc3321179d81ae7388562bb6c54db616db87d0b Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Tue, 19 Mar 2024 15:51:47 -0700 Subject: [PATCH 022/113] ARM: dts: msm: Add lowSVS_D3 power level to Sun GPU Add supported lower power level to Sun GPU. Change-Id: I896fe7cd45d1b1a824d3a0d7c47115952d8598ea Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 5f15d4bd..38f67d72 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -31,6 +31,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <10>; + qcom,initial-min-pwrlevel = <10>; qcom,sku-codes = ; @@ -176,6 +177,17 @@ qcom,acd-level = ; }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <125000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; }; qcom,gpu-pwrlevels-1 { @@ -183,6 +195,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; + qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; /* TURBO_L3 */ @@ -353,6 +366,17 @@ qcom,acd-level = ; }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <125000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; }; }; }; From cb1a9008b35a4133536f7f641b5be12d53b7c2ea Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Tue, 5 Mar 2024 10:23:28 -0800 Subject: [PATCH 023/113] ARM: dts: msm: Add turbo_l4 power level to Sun GPU Add supported higher power level to Sun GPU. Change-Id: Icfbdae6f7b44edea00fbf3374224cb407bd0968d Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 72 +++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 29 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 38f67d72..4e8c09c1 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -4,6 +4,7 @@ */ /* ACD Control register values */ +#define ACD_LEVEL_TURBO_L4 0x802e5ffd #define ACD_LEVEL_TURBO_L3 0xa02f5ffd #define ACD_LEVEL_TURBO_L1 0xa8285ffd #define ACD_LEVEL_NOM_L1 0x88295ffd @@ -194,13 +195,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; - qcom,initial-min-pwrlevel = <12>; + qcom,initial-pwrlevel = <13>; + qcom,initial-min-pwrlevel = <13>; qcom,sku-codes = ; - /* TURBO_L3 */ + /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -212,8 +226,8 @@ }; /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -225,8 +239,8 @@ }; /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -238,8 +252,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -251,8 +265,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <779000000>; qcom,level = ; @@ -264,8 +278,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -277,8 +291,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -290,8 +304,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -303,8 +317,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -316,8 +330,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -329,8 +343,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -342,8 +356,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -355,8 +369,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -368,8 +382,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; + qcom,gpu-pwrlevel@14 { + reg = <14>; qcom,gpu-freq = <125000000>; qcom,level = ; From 69ade8a5f00c24f4224aa56d782ec5c6ef572ecc Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Fri, 8 Mar 2024 10:25:45 -0800 Subject: [PATCH 024/113] ARM: dts: msm: Update ACD values for Sun GPU Update ACD control register values with characterized values. Change-Id: I6e605b578db6da4d31e28e5fadc1bad991a2d9d1 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 4e8c09c1..41adb786 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -4,20 +4,20 @@ */ /* ACD Control register values */ -#define ACD_LEVEL_TURBO_L4 0x802e5ffd -#define ACD_LEVEL_TURBO_L3 0xa02f5ffd -#define ACD_LEVEL_TURBO_L1 0xa8285ffd -#define ACD_LEVEL_NOM_L1 0x88295ffd -#define ACD_LEVEL_NOM 0x88295ffd -#define ACD_LEVEL_SVS_L2 0x882a5ffd -#define ACD_LEVEL_SVS_L1 0x882a5ffd -#define ACD_LEVEL_SVS_L0 0xa82b5ffd -#define ACD_LEVEL_SVS 0xa82c5ffd -#define ACD_LEVEL_LOW_SVS_L1 0x882e5ffd -#define ACD_LEVEL_LOW_SVS 0xc0295ffd -#define ACD_LEVEL_LOW_SVS_D0 0xc02a5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xc02b5ffd -#define ACD_LEVEL_LOW_SVS_D2 0xe8285ffd +#define ACD_LEVEL_TURBO_L4 0x88295ffd +#define ACD_LEVEL_TURBO_L3 0x882a5ffd +#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0x882b5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS_L0 0x882d5ffd +#define ACD_LEVEL_SVS 0xa82e5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd +#define ACD_LEVEL_LOW_SVS 0xe02d5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd +#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd &msm_gpu { /* Power levels */ From 564471dede9eda4d761c97aa97811d485fffbab3 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Tue, 13 Feb 2024 01:47:52 +0530 Subject: [PATCH 025/113] ARM: dts: msm: Add power domains for sun GPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GDSCs were modeled as regulators till now. However, moving forward, GDSCs will be treated as power domains. Consequently, replace references to ‘regulators’ with ‘power domains’ for the sun GPU. Change-Id: I607a511754d56728d5013004d0ae83544f873df6 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dts | 3 ++- gpu/sun-gpu.dtsi | 9 ++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index eda85863..e0cc7986 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 548a1bb0..21cbd14d 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -136,7 +136,7 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x3da0000 0x40000>; - vddcx-supply = <&gpu_cc_cx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -169,10 +169,9 @@ <0 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - regulator-names = "vddcx", "vdd"; - - vddcx-supply = <&gpu_cc_cx_gdsc>; - vdd-supply = <&gx_clkctl_gx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From 669e9df2ea76a84551666011cffaffdaaeec34ef Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Fri, 29 Mar 2024 15:21:29 -0600 Subject: [PATCH 026/113] ARM: dts: msm: Add additional Sun GPU msm-id support Add new msm-id support for Sun GPU V1. Change-Id: I38eeabb8a13ac533b76abfb26f0faa81214f36bf Signed-off-by: Carter Cooper --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index eda85863..26c509a4 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,msm-id = <0x26a 0x10000>, <0x27f 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>; qcom,board-id = <0 0>; }; From 5641f98ed82df2fff798fac50f628251f09d3212 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Tue, 12 Mar 2024 14:40:49 -0600 Subject: [PATCH 027/113] ARM: dts: msm: Add Sun V2 GPU support Add GPU support for Sun V2 devices. Change-Id: I8fab9d400ace2257e486fadc5e41836013e09c77 Signed-off-by: Carter Cooper --- Kbuild | 3 +- gpu/sun-v2-gpu-pwrlevels.dtsi | 369 ++++++++++++++++++++++++++++++++++ gpu/sun-v2-gpu.dts | 27 +++ gpu/sun-v2-gpu.dtsi | 14 ++ 4 files changed, 412 insertions(+), 1 deletion(-) create mode 100644 gpu/sun-v2-gpu-pwrlevels.dtsi create mode 100644 gpu/sun-v2-gpu.dts create mode 100644 gpu/sun-v2-gpu.dtsi diff --git a/Kbuild b/Kbuild index 82161dd3..da849afb 100644 --- a/Kbuild +++ b/Kbuild @@ -4,7 +4,8 @@ dtbo-y += gpu/pineapple-gpu.dtbo \ endif ifeq ($(CONFIG_ARCH_SUN), y) -dtbo-y += gpu/sun-gpu.dtbo +dtbo-y += gpu/sun-gpu.dtbo \ + gpu/sun-v2-gpu.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..8d44b096 --- /dev/null +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L3 0x882a5ffd +#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0x882b5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS_L0 0x882d5ffd +#define ACD_LEVEL_SVS 0xa82e5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd +#define ACD_LEVEL_LOW_SVS 0xe02d5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd +#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd + +&msm_gpu { + /* Power levels */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <9>; + qcom,initial-min-pwrlevel = <9>; + qcom,sku-codes = ; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <12>; + qcom,initial-min-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + }; +}; diff --git a/gpu/sun-v2-gpu.dts b/gpu/sun-v2-gpu.dts new file mode 100644 index 00000000..662cfb91 --- /dev/null +++ b/gpu/sun-v2-gpu.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sun-v2-gpu.dtsi" +#include "sun-v2-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sun"; + compatible = "qcom,sun"; + qcom,msm-id = <0x26a 0x20000>, <0x27f 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/sun-v2-gpu.dtsi b/gpu/sun-v2-gpu.dtsi new file mode 100644 index 00000000..b9366d3f --- /dev/null +++ b/gpu/sun-v2-gpu.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-gpu.dtsi" + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen8-0-1", "qcom,kgsl-3d0"; + + qcom,gpu-model = "Adreno830v2"; + + qcom,chipid = <0x44050001>; +}; From 051ac8e2120f7e9d88291e00c046b292b5a18c79 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Tue, 12 Mar 2024 14:40:49 -0600 Subject: [PATCH 028/113] ARM: dts: msm: Add Sun V2 GPU support Add GPU support for Sun V2 devices. Signed-off-by: Carter Cooper Change-Id: I8fab9d400ace2257e486fadc5e41836013e09c77 --- Kbuild | 3 +- gpu/sun-v2-gpu-pwrlevels.dtsi | 369 ++++++++++++++++++++++++++++++++++ gpu/sun-v2-gpu.dts | 26 +++ gpu/sun-v2-gpu.dtsi | 14 ++ 4 files changed, 411 insertions(+), 1 deletion(-) create mode 100644 gpu/sun-v2-gpu-pwrlevels.dtsi create mode 100644 gpu/sun-v2-gpu.dts create mode 100644 gpu/sun-v2-gpu.dtsi diff --git a/Kbuild b/Kbuild index 82161dd3..da849afb 100644 --- a/Kbuild +++ b/Kbuild @@ -4,7 +4,8 @@ dtbo-y += gpu/pineapple-gpu.dtbo \ endif ifeq ($(CONFIG_ARCH_SUN), y) -dtbo-y += gpu/sun-gpu.dtbo +dtbo-y += gpu/sun-gpu.dtbo \ + gpu/sun-v2-gpu.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..8d44b096 --- /dev/null +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L3 0x882a5ffd +#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0x882b5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS_L0 0x882d5ffd +#define ACD_LEVEL_SVS 0xa82e5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd +#define ACD_LEVEL_LOW_SVS 0xe02d5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd +#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd + +&msm_gpu { + /* Power levels */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <9>; + qcom,initial-min-pwrlevel = <9>; + qcom,sku-codes = ; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <12>; + qcom,initial-min-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + }; +}; diff --git a/gpu/sun-v2-gpu.dts b/gpu/sun-v2-gpu.dts new file mode 100644 index 00000000..f317c536 --- /dev/null +++ b/gpu/sun-v2-gpu.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sun-v2-gpu.dtsi" +#include "sun-v2-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sun"; + compatible = "qcom,sun"; + qcom,msm-id = <0x26a 0x20000>, <0x27f 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/sun-v2-gpu.dtsi b/gpu/sun-v2-gpu.dtsi new file mode 100644 index 00000000..b9366d3f --- /dev/null +++ b/gpu/sun-v2-gpu.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-gpu.dtsi" + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen8-0-1", "qcom,kgsl-3d0"; + + qcom,gpu-model = "Adreno830v2"; + + qcom,chipid = <0x44050001>; +}; From 43c1c5228442978c331378bdd1806b058c188fa8 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Fri, 29 Mar 2024 15:21:29 -0600 Subject: [PATCH 029/113] ARM: dts: msm: Add additional Sun GPU msm-id support Add new msm-id support for Sun GPU V1. Change-Id: I38eeabb8a13ac533b76abfb26f0faa81214f36bf Signed-off-by: Carter Cooper --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index eda85863..26c509a4 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,msm-id = <0x26a 0x10000>, <0x27f 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>; qcom,board-id = <0 0>; }; From e75484bfe26fe6dbb6a7493aee6aca90ccb3634f Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Tue, 14 May 2024 02:03:32 -0700 Subject: [PATCH 030/113] Revert "ARM: dts: msm: Add additional Sun GPU msm-id support" This reverts commit 43c1c5228442978c331378bdd1806b058c188fa8. Change-Id: I276e34d1019a875d5cdc7e60f96dcd28f0baa921 Signed-off-by: Linux Image Build Automation --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index 26c509a4..eda85863 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <0x26a 0x10000>, <0x27f 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>; + qcom,msm-id = <618 0x10000>, <639 0x10000>; qcom,board-id = <0 0>; }; From db52b9a9d59250b43da8976108df6e84b9b528ed Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Tue, 14 May 2024 02:03:45 -0700 Subject: [PATCH 031/113] Revert "ARM: dts: msm: Add Sun V2 GPU support" This reverts commit 051ac8e2120f7e9d88291e00c046b292b5a18c79. Change-Id: I5ae810d6ef65811facd34c52e955bf71404b2458 Signed-off-by: Linux Image Build Automation --- Kbuild | 3 +- gpu/sun-v2-gpu-pwrlevels.dtsi | 369 ---------------------------------- gpu/sun-v2-gpu.dts | 26 --- gpu/sun-v2-gpu.dtsi | 14 -- 4 files changed, 1 insertion(+), 411 deletions(-) delete mode 100644 gpu/sun-v2-gpu-pwrlevels.dtsi delete mode 100644 gpu/sun-v2-gpu.dts delete mode 100644 gpu/sun-v2-gpu.dtsi diff --git a/Kbuild b/Kbuild index da849afb..82161dd3 100644 --- a/Kbuild +++ b/Kbuild @@ -4,8 +4,7 @@ dtbo-y += gpu/pineapple-gpu.dtbo \ endif ifeq ($(CONFIG_ARCH_SUN), y) -dtbo-y += gpu/sun-gpu.dtbo \ - gpu/sun-v2-gpu.dtbo +dtbo-y += gpu/sun-gpu.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi deleted file mode 100644 index 8d44b096..00000000 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/* ACD Control register values */ -#define ACD_LEVEL_TURBO_L3 0x882a5ffd -#define ACD_LEVEL_TURBO_L1 0x882a5ffd -#define ACD_LEVEL_NOM_L1 0x882b5ffd -#define ACD_LEVEL_NOM 0x882b5ffd -#define ACD_LEVEL_SVS_L2 0x882b5ffd -#define ACD_LEVEL_SVS_L1 0xa82b5ffd -#define ACD_LEVEL_SVS_L0 0x882d5ffd -#define ACD_LEVEL_SVS 0xa82e5ffd -#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd -#define ACD_LEVEL_LOW_SVS 0xe02d5ffd -#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd -#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd - -&msm_gpu { - /* Power levels */ - qcom,gpu-pwrlevel-bins { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qcom,gpu-pwrlevels-bins"; - - qcom,gpu-pwrlevels-0 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <9>; - qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; - - /* NOM */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <2>; - qcom,bus-min = <2>; - qcom,bus-max = <2>; - }; - }; - - qcom,gpu-pwrlevels-1 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <12>; - qcom,initial-min-pwrlevel = <12>; - qcom,sku-codes = ; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <10>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <2>; - qcom,bus-min = <2>; - qcom,bus-max = <2>; - }; - }; - }; -}; diff --git a/gpu/sun-v2-gpu.dts b/gpu/sun-v2-gpu.dts deleted file mode 100644 index f317c536..00000000 --- a/gpu/sun-v2-gpu.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sun-v2-gpu.dtsi" -#include "sun-v2-gpu-pwrlevels.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. sun"; - compatible = "qcom,sun"; - qcom,msm-id = <0x26a 0x20000>, <0x27f 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>; - qcom,board-id = <0 0>; -}; diff --git a/gpu/sun-v2-gpu.dtsi b/gpu/sun-v2-gpu.dtsi deleted file mode 100644 index b9366d3f..00000000 --- a/gpu/sun-v2-gpu.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include "sun-gpu.dtsi" - -&msm_gpu { - compatible = "qcom,adreno-gpu-gen8-0-1", "qcom,kgsl-3d0"; - - qcom,gpu-model = "Adreno830v2"; - - qcom,chipid = <0x44050001>; -}; From c4fbe9585195f1aa220b4c9015f5e16b46b78c43 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 16 May 2024 08:36:47 -0700 Subject: [PATCH 032/113] ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun Update bus votes for LOW_SVS_D1 corner to have the better power savings. Change-Id: I91872df0dffd1be77d53f6b04bc1296163a1e5fa Signed-off-by: Hareesh Gundu --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 41adb786..5308184d 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 8d44b096..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; From 2992daffa03ea2ec1f776d481bf23cb5f021b7df Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 16 May 2024 08:36:47 -0700 Subject: [PATCH 033/113] ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun Update bus votes for LOW_SVS_D1 corner to have the better power savings. Change-Id: I91872df0dffd1be77d53f6b04bc1296163a1e5fa Signed-off-by: Hareesh Gundu --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 41adb786..5308184d 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 8d44b096..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; From 78fe37ca23c6f9955f998aa319170e98e5a03d5a Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 14:24:33 -0600 Subject: [PATCH 034/113] ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan Update the frequency tables for AB and AC SKUs. Change-Id: I46b22a1ccf28db9bc40ea00483d17f4f97b6c6d4 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +++++++++++++++++++++++++++++++++- 1 file changed, 177 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..995091c4 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,8 +32,7 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -181,6 +180,182 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <11>; + qcom,initial-min-pwrlevel = <11>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From bd5166fd80d58aebc3011dec05d287266ad252a4 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 14:24:33 -0600 Subject: [PATCH 035/113] ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan Update the frequency tables for AB and AC SKUs. Change-Id: I46b22a1ccf28db9bc40ea00483d17f4f97b6c6d4 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +++++++++++++++++++++++++++++++++- 1 file changed, 177 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..995091c4 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,8 +32,7 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -181,6 +180,182 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <11>; + qcom,initial-min-pwrlevel = <11>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From 93a916817e9ea3405d5cda5561a0db627422a771 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Mon, 3 Jun 2024 16:29:56 -0700 Subject: [PATCH 036/113] Revert "ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan" This reverts commit 78fe37ca23c6f9955f998aa319170e98e5a03d5a. Change-Id: Ie7b89cef0841c79e59b7e8501efec54b5f1a4278 Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +--------------------------------- 1 file changed, 2 insertions(+), 177 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 995091c4..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,7 +32,8 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -180,182 +181,6 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; - qcom,initial-min-pwrlevel = <11>; - qcom,sku-codes = ; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <2>; - qcom,bus-min = <2>; - qcom,bus-max = <2>; - }; - }; - - qcom,gpu-pwrlevels-2 { - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From 3ff5b62e77ca4f8ba5143155aa5b1a5c861e0d2c Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Mon, 3 Jun 2024 16:30:08 -0700 Subject: [PATCH 037/113] Revert "ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun" This reverts commit 2992daffa03ea2ec1f776d481bf23cb5f021b7df. Change-Id: Icf6ec170d12db836beef7ea144ce6c36d295ecd5 Signed-off-by: Linux Image Build Automation --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 5308184d..41adb786 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..8d44b096 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; From 3a579891a4112aa90f0243f4a3311fe69fa97d82 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 16 May 2024 08:36:47 -0700 Subject: [PATCH 038/113] ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun Update bus votes for LOW_SVS_D1 corner to have the better power savings. Change-Id: Iff8e95bbab16427c94b87775fb69d28e0bf9154d Signed-off-by: Hareesh Gundu --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 41adb786..5308184d 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 8d44b096..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; From 4fe74b97685315bdaff0f058e5e222388bc8ad56 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 14:24:33 -0600 Subject: [PATCH 039/113] ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan Update the frequency tables for AB and AC SKUs. Change-Id: I74ca8d69d9584b98e36c8aacd39d0b435cf15154 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +++++++++++++++++++++++++++++++++- 1 file changed, 177 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..995091c4 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,8 +32,7 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -181,6 +180,182 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <11>; + qcom,initial-min-pwrlevel = <11>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From 9cbd03668a8b435f9a5260037f0eec0f0833f510 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 13:53:45 -0600 Subject: [PATCH 040/113] ARM: dts: msm: Remove Sun V2 thermal only GPU frequencies All lower GPU frequencies are available and the lowest frequency is no longer considered 'thermal only'. Remove the tag to allow the lowest GPU frequency as a normal corner for Sun V2. Change-Id: I3c2384a0d8d107393d71a3dbf8c22090304e64a7 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 995091c4..7a70ac8d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -30,8 +30,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; - qcom,initial-min-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,sku-codes = ; /* NOM */ @@ -170,9 +169,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <2>; + qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <2>; + qcom,bus-max = <3>; }; }; @@ -180,8 +179,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; - qcom,initial-min-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,sku-codes = ; /* TURBO_L1 */ @@ -346,9 +344,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <2>; + qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <2>; + qcom,bus-max = <3>; }; }; @@ -356,8 +354,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; - qcom,initial-min-pwrlevel = <12>; + qcom,initial-pwrlevel = <13>; qcom,sku-codes = ; /* TURBO_L3 */ @@ -535,9 +532,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <2>; + qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <2>; + qcom,bus-max = <3>; }; }; }; From 48b0e9aa4476e3477904d05522b9d3a61bf9ac1f Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 13:51:01 -0600 Subject: [PATCH 041/113] ARM: dts: msm: Update Sun V2 GPU frequencies Add new GPU frequency support for Sun V2. Change-Id: I66a6584a671e51a8420e2ceaace3c067ee56d009 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 72 +++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 29 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 7a70ac8d..3418c791 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -4,6 +4,7 @@ */ /* ACD Control register values */ +#define ACD_LEVEL_TURBO_L4 0x88295ffd #define ACD_LEVEL_TURBO_L3 0x882a5ffd #define ACD_LEVEL_TURBO_L1 0x882a5ffd #define ACD_LEVEL_NOM_L1 0x882b5ffd @@ -354,13 +355,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; - /* TURBO_L3 */ + /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1150000000>; + qcom,gpu-freq = <1200000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -371,8 +385,8 @@ }; /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -384,8 +398,8 @@ }; /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -397,8 +411,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -410,8 +424,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -423,8 +437,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -436,8 +450,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -449,8 +463,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -462,8 +476,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -475,8 +489,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -488,8 +502,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -501,8 +515,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -514,8 +528,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -527,8 +541,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; + qcom,gpu-pwrlevel@14 { + reg = <14>; qcom,gpu-freq = <160000000>; qcom,level = ; From 24406b833c59ec41815c38cd979aed15d3cbf7fd Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 3 Jun 2024 10:11:34 -0700 Subject: [PATCH 042/113] ARM: dts: msm: Read the gpu speed bin on sun devices Read the gpu speed bin devicetree property on sun devices. Change-Id: I54c444bc434a2475ffe5126b7452f642f4dc7b2a Signed-off-by: Lynus Vaz --- gpu/sun-gpu.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 34c90a61..a3e97828 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -83,6 +83,9 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L3 index=11 */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; From 8c6526dcaa74b5c955e0d36a12a23ba8638da7af Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Wed, 5 Jun 2024 22:31:35 -0700 Subject: [PATCH 043/113] ARM: dts: msm: Update ACD values for Sun v2 GPU Update ACD values with characterized values for Sun v2 GPU. Also disable ACD on lower levels. Change-Id: Ic5f0d7adb7a71be16f393ff90a6d0199179276a3 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-v2-gpu-pwrlevels.dtsi | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 3418c791..cd161ec7 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -5,19 +5,17 @@ /* ACD Control register values */ #define ACD_LEVEL_TURBO_L4 0x88295ffd -#define ACD_LEVEL_TURBO_L3 0x882a5ffd -#define ACD_LEVEL_TURBO_L1 0x882a5ffd -#define ACD_LEVEL_NOM_L1 0x882b5ffd -#define ACD_LEVEL_NOM 0x882b5ffd -#define ACD_LEVEL_SVS_L2 0x882b5ffd -#define ACD_LEVEL_SVS_L1 0xa82b5ffd -#define ACD_LEVEL_SVS_L0 0x882d5ffd +#define ACD_LEVEL_TURBO_L3 0x88295ffd +#define ACD_LEVEL_TURBO_L1 0xa8295ffd +#define ACD_LEVEL_NOM_L1 0x882a5ffd +#define ACD_LEVEL_NOM 0x882a5ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0xa82a5ffd +#define ACD_LEVEL_SVS_L0 0x882c5ffd #define ACD_LEVEL_SVS 0xa82e5ffd -#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd -#define ACD_LEVEL_LOW_SVS 0xe02d5ffd -#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd -#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc02e5ffd +#define ACD_LEVEL_LOW_SVS 0xc02e5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xc8285ffd &msm_gpu { /* Power levels */ @@ -147,8 +145,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -160,8 +156,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -322,8 +316,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -335,8 +327,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -523,8 +513,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -536,8 +524,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ From 2a80873bf1ab670c5d062ccad5ca4540ffff2016 Mon Sep 17 00:00:00 2001 From: Bruce Levy Date: Tue, 18 Jun 2024 23:04:09 -0700 Subject: [PATCH 044/113] Revert "ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan" This reverts commit 4fe74b97685315bdaff0f058e5e222388bc8ad56. Signed-off-by: Bruce Levy Change-Id: If4dd9a1ba8ae7d5e8f2ed24a9acede3057b446fa --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +--------------------------------- 1 file changed, 2 insertions(+), 177 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 995091c4..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,7 +32,8 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -180,182 +181,6 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; - qcom,initial-min-pwrlevel = <11>; - qcom,sku-codes = ; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <2>; - qcom,bus-min = <2>; - qcom,bus-max = <2>; - }; - }; - - qcom,gpu-pwrlevels-2 { - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From 127483cf3fed7c84e23574a1eb374951972bac02 Mon Sep 17 00:00:00 2001 From: Bruce Levy Date: Tue, 18 Jun 2024 23:04:12 -0700 Subject: [PATCH 045/113] Revert "ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun" This reverts commit 3a579891a4112aa90f0243f4a3311fe69fa97d82. Signed-off-by: Bruce Levy Change-Id: I85222624406eb4a2fb52a0ff3e6e320b89a56b53 --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 5308184d..41adb786 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..8d44b096 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; From 361c4aa3498c9f35f766e14d40e10cf3f3fef779 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Wed, 12 Jun 2024 12:00:01 -0700 Subject: [PATCH 046/113] ARM: dts: msm: Use the speed bin fuse to determine sun v2 powerlevels Add powerlevels on sun v2 GPUs based on the speed bin fuse on the device. Change-Id: Ia0b35aabce36ab210ed01ea3c8abb90c05e74ac6 Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 547 +++++++++++++++++++++++++++++++++- 1 file changed, 545 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index cd161ec7..df211154 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -25,12 +25,16 @@ compatible = "qcom,gpu-pwrlevels-bins"; + /* + * The bins need to match based on speed bin first and then SKU. + * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. + */ qcom,gpu-pwrlevels-0 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <10>; - qcom,sku-codes = ; + qcom,speed-bin = <0xbe>; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -175,7 +179,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,speed-bin = <0xdd>; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { @@ -345,6 +349,545 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,speed-bin = <0xf2>; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; From 104705ce03cb699f54c93b9e81df9fed23d2ab2e Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 16 May 2024 08:36:47 -0700 Subject: [PATCH 047/113] ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun Update bus votes for LOW_SVS_D1 corner to have the better power savings. Signed-off-by: Hareesh Gundu Signed-off-by: Xhoendi Collaku Change-Id: If0bbb204446d98117264dde29622c43cfc9058d0 --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 41adb786..5308184d 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 8d44b096..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <6>; + qcom,bus-max = <3>; qcom,acd-level = ; }; From ffe4d3c206ba04da12b5671e1d9ad17e44be9c16 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 14:24:33 -0600 Subject: [PATCH 048/113] ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan Update the frequency tables for AB and AC SKUs. Signed-off-by: Carter Cooper Signed-off-by: Xhoendi Collaku Change-Id: I0b19eb8cbb4867ac565fe7c8f381b1c2ba1e3c76 Signed-off-by: Xhoendi Collaku --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +++++++++++++++++++++++++++++++++- 1 file changed, 177 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..995091c4 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,8 +32,7 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -181,6 +180,182 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <11>; + qcom,initial-min-pwrlevel = <11>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <2>; + qcom,bus-min = <2>; + qcom,bus-max = <2>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From e718fd3680b91212ecfc6c21f62cb89646e90877 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 24 Jun 2024 19:59:35 -0700 Subject: [PATCH 049/113] ARM: dts: msm: Update Sun v2 GPU power levels Add more powerlevel bins based on updated speed-bin fuse values. Change-Id: I4faf67ffad06ba5873c0e9879b7729f796952d3a Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 368 ++++++++++++++++------------------ 1 file changed, 178 insertions(+), 190 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index df211154..c299542b 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -350,19 +350,19 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,speed-bin = <0xe8>; - /* TURBO_L1 */ + /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; + qcom,gpu-freq = <1100000000>; + qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; - qcom,acd-level = ; + qcom,acd-level = ; }; /* NOM_L1 */ @@ -520,6 +520,177 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1100000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <13>; qcom,speed-bin = <0xf2>; @@ -700,196 +871,13 @@ }; }; - qcom,gpu-pwrlevels-4 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <13>; - qcom,sku-codes = ; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - qcom,gpu-pwrlevels-5 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <14>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { From 06cbe225fabd0adc987ac023fce13dbff817e949 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 13:53:45 -0600 Subject: [PATCH 050/113] ARM: dts: msm: Remove Sun V2 thermal only GPU frequencies All lower GPU frequencies are available and the lowest frequency is no longer considered 'thermal only'. Remove the tag to allow the lowest GPU frequency as a normal corner for Sun V2. Change-Id: I3c2384a0d8d107393d71a3dbf8c22090304e64a7 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 995091c4..7a70ac8d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -30,8 +30,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; - qcom,initial-min-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,sku-codes = ; /* NOM */ @@ -170,9 +169,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <2>; + qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <2>; + qcom,bus-max = <3>; }; }; @@ -180,8 +179,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; - qcom,initial-min-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,sku-codes = ; /* TURBO_L1 */ @@ -346,9 +344,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <2>; + qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <2>; + qcom,bus-max = <3>; }; }; @@ -356,8 +354,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; - qcom,initial-min-pwrlevel = <12>; + qcom,initial-pwrlevel = <13>; qcom,sku-codes = ; /* TURBO_L3 */ @@ -535,9 +532,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <2>; + qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <2>; + qcom,bus-max = <3>; }; }; }; From 7fbfbf06b73007c1304fe4329e9264fd6bf3d323 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 3 Jul 2024 13:35:24 -0700 Subject: [PATCH 051/113] Revert "ARM: dts: msm: Remove Sun V2 thermal only GPU frequencies" This reverts commit 06cbe225fabd0adc987ac023fce13dbff817e949. Change-Id: Ia0c36ac50cd2a9f8fc3ab823d9625c3c09ad5b8a Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 7a70ac8d..995091c4 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -30,7 +30,8 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <10>; + qcom,initial-pwrlevel = <9>; + qcom,initial-min-pwrlevel = <9>; qcom,sku-codes = ; /* NOM */ @@ -169,9 +170,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -179,7 +180,8 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; + qcom,initial-min-pwrlevel = <11>; qcom,sku-codes = ; /* TURBO_L1 */ @@ -344,9 +346,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -354,7 +356,8 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <12>; + qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; /* TURBO_L3 */ @@ -532,9 +535,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; }; From da7da2351eabc346080ec8316047bd4f08956770 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 3 Jul 2024 13:42:03 -0700 Subject: [PATCH 052/113] Revert "ARM: dts: msm: Update Sun V2 GPU external SKU frequency plan" This reverts commit ffe4d3c206ba04da12b5671e1d9ad17e44be9c16. Change-Id: Ie5c8dbc03629255b1ad44813fbb84ba31081f6fd Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 179 +--------------------------------- 1 file changed, 2 insertions(+), 177 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 995091c4..f79d8b73 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -32,7 +32,8 @@ qcom,initial-pwrlevel = <9>; qcom,initial-min-pwrlevel = <9>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -180,182 +181,6 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; - qcom,initial-min-pwrlevel = <11>; - qcom,sku-codes = ; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <2>; - qcom,bus-min = <2>; - qcom,bus-max = <2>; - }; - }; - - qcom,gpu-pwrlevels-2 { - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <12>; qcom,initial-min-pwrlevel = <12>; qcom,sku-codes = ; From e5bce453eecefd28d2345a65a8fa758a80fb44d4 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 3 Jul 2024 13:42:16 -0700 Subject: [PATCH 053/113] Revert "ARM: dts: msm: Update LOW_SVS_D1 bus votes for sun" This reverts commit 104705ce03cb699f54c93b9e81df9fed23d2ab2e. Change-Id: I998d09ee8be103980f7ed35661c435da4813aa39 Signed-off-by: Linux Image Build Automation --- gpu/sun-gpu-pwrlevels.dtsi | 4 ++-- gpu/sun-v2-gpu-pwrlevels.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 5308184d..41adb786 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -161,7 +161,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; @@ -363,7 +363,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index f79d8b73..8d44b096 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -147,7 +147,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; @@ -336,7 +336,7 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <6>; qcom,acd-level = ; }; From 6a4b833d28b64d5b1733c746643c5870e01ddef2 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 8 Jul 2024 11:30:43 -0700 Subject: [PATCH 054/113] ARM: dts: msm: Add more SKUs to the Sun v2 powerlevels Add the AA SKU to the Sun v2 powerlevels so that it is recognized and selects the appropriate powerlevel table. Change-Id: I5bb706e3477efa390a8b40d24f85daabe111a0b8 Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index c299542b..da69ba0d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -521,7 +521,8 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { From 154f54c2c999638fe6852cb72ec779111d59ce42 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 13:51:01 -0600 Subject: [PATCH 055/113] ARM: dts: msm: Update Sun V2 GPU frequencies Add new GPU frequency support for Sun V2. Change-Id: I66a6584a671e51a8420e2ceaace3c067ee56d009 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 72 +++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 29 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 7a70ac8d..3418c791 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -4,6 +4,7 @@ */ /* ACD Control register values */ +#define ACD_LEVEL_TURBO_L4 0x88295ffd #define ACD_LEVEL_TURBO_L3 0x882a5ffd #define ACD_LEVEL_TURBO_L1 0x882a5ffd #define ACD_LEVEL_NOM_L1 0x882b5ffd @@ -354,13 +355,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; - /* TURBO_L3 */ + /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1150000000>; + qcom,gpu-freq = <1200000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -371,8 +385,8 @@ }; /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -384,8 +398,8 @@ }; /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -397,8 +411,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -410,8 +424,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -423,8 +437,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -436,8 +450,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -449,8 +463,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -462,8 +476,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -475,8 +489,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -488,8 +502,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -501,8 +515,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -514,8 +528,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -527,8 +541,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; + qcom,gpu-pwrlevel@14 { + reg = <14>; qcom,gpu-freq = <160000000>; qcom,level = ; From 7f2973e909333304c66ee8db3484c75abbaa0ab6 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Wed, 5 Jun 2024 22:31:35 -0700 Subject: [PATCH 056/113] ARM: dts: msm: Update ACD values for Sun v2 GPU Update ACD values with characterized values for Sun v2 GPU. Also disable ACD on lower levels. Change-Id: Ic5f0d7adb7a71be16f393ff90a6d0199179276a3 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-v2-gpu-pwrlevels.dtsi | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 3418c791..cd161ec7 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -5,19 +5,17 @@ /* ACD Control register values */ #define ACD_LEVEL_TURBO_L4 0x88295ffd -#define ACD_LEVEL_TURBO_L3 0x882a5ffd -#define ACD_LEVEL_TURBO_L1 0x882a5ffd -#define ACD_LEVEL_NOM_L1 0x882b5ffd -#define ACD_LEVEL_NOM 0x882b5ffd -#define ACD_LEVEL_SVS_L2 0x882b5ffd -#define ACD_LEVEL_SVS_L1 0xa82b5ffd -#define ACD_LEVEL_SVS_L0 0x882d5ffd +#define ACD_LEVEL_TURBO_L3 0x88295ffd +#define ACD_LEVEL_TURBO_L1 0xa8295ffd +#define ACD_LEVEL_NOM_L1 0x882a5ffd +#define ACD_LEVEL_NOM 0x882a5ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0xa82a5ffd +#define ACD_LEVEL_SVS_L0 0x882c5ffd #define ACD_LEVEL_SVS 0xa82e5ffd -#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd -#define ACD_LEVEL_LOW_SVS 0xe02d5ffd -#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd -#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc02e5ffd +#define ACD_LEVEL_LOW_SVS 0xc02e5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xc8285ffd &msm_gpu { /* Power levels */ @@ -147,8 +145,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -160,8 +156,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -322,8 +316,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -335,8 +327,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -523,8 +513,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -536,8 +524,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ From 243ac95d778d23d6e5d46200cfd4d58cf1eb4ad3 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Wed, 12 Jun 2024 12:00:01 -0700 Subject: [PATCH 057/113] ARM: dts: msm: Use the speed bin fuse to determine sun v2 powerlevels Add powerlevels on sun v2 GPUs based on the speed bin fuse on the device. Change-Id: Ia0b35aabce36ab210ed01ea3c8abb90c05e74ac6 Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 547 +++++++++++++++++++++++++++++++++- 1 file changed, 545 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index cd161ec7..df211154 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -25,12 +25,16 @@ compatible = "qcom,gpu-pwrlevels-bins"; + /* + * The bins need to match based on speed bin first and then SKU. + * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. + */ qcom,gpu-pwrlevels-0 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <10>; - qcom,sku-codes = ; + qcom,speed-bin = <0xbe>; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -175,7 +179,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,speed-bin = <0xdd>; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { @@ -345,6 +349,545 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,speed-bin = <0xf2>; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; From b2bd3d7a6de65cd8067a40525e06ba8a871ffd6b Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 24 Jun 2024 19:59:35 -0700 Subject: [PATCH 058/113] ARM: dts: msm: Update Sun v2 GPU power levels Add more powerlevel bins based on updated speed-bin fuse values. Change-Id: I4faf67ffad06ba5873c0e9879b7729f796952d3a Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 368 ++++++++++++++++------------------ 1 file changed, 178 insertions(+), 190 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index df211154..c299542b 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -350,19 +350,19 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,speed-bin = <0xe8>; - /* TURBO_L1 */ + /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; + qcom,gpu-freq = <1100000000>; + qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; - qcom,acd-level = ; + qcom,acd-level = ; }; /* NOM_L1 */ @@ -520,6 +520,177 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1100000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <13>; qcom,speed-bin = <0xf2>; @@ -700,196 +871,13 @@ }; }; - qcom,gpu-pwrlevels-4 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <13>; - qcom,sku-codes = ; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - qcom,gpu-pwrlevels-5 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <14>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { From 87220e2e950ebb1751f992104e4beef76dc24fed Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 3 Jun 2024 10:11:34 -0700 Subject: [PATCH 059/113] ARM: dts: msm: Read the gpu speed bin on sun devices Read the gpu speed bin devicetree property on sun devices. Change-Id: I54c444bc434a2475ffe5126b7452f642f4dc7b2a Signed-off-by: Lynus Vaz --- gpu/sun-gpu.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 34c90a61..a3e97828 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -83,6 +83,9 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L3 index=11 */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; From eb96d382eb40162bf6643f571012b17a0d602fc0 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 17 Jul 2024 01:29:29 -0700 Subject: [PATCH 060/113] Revert "ARM: dts: msm: Read the gpu speed bin on sun devices" This reverts commit 87220e2e950ebb1751f992104e4beef76dc24fed. Change-Id: I7315a736fc914d475d54060193526958dc869007 Signed-off-by: Linux Image Build Automation --- gpu/sun-gpu.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index a3e97828..34c90a61 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -83,9 +83,6 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L3 index=11 */ - nvmem-cells = <&gpu_speed_bin>; - nvmem-cell-names = "speed_bin"; - zap-shader { memory-region = <&gpu_microcode_mem>; }; From 8106ee0f688c91e8f329fde43d6382b63d220c45 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 17 Jul 2024 01:29:41 -0700 Subject: [PATCH 061/113] Revert "ARM: dts: msm: Update Sun v2 GPU power levels" This reverts commit b2bd3d7a6de65cd8067a40525e06ba8a871ffd6b. Change-Id: I56502b5d3035c18bd8c8a04cf00f76d22b552f25 Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 368 ++++++++++++++++++---------------- 1 file changed, 190 insertions(+), 178 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index c299542b..df211154 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -350,19 +350,19 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,speed-bin = <0xe8>; + qcom,sku-codes = ; - /* TURBO_L3 */ + /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1100000000>; - qcom,level = ; + qcom,gpu-freq = <1050000000>; + qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; - qcom,acd-level = ; + qcom,acd-level = ; }; /* NOM_L1 */ @@ -520,177 +520,6 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1100000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - - qcom,gpu-pwrlevels-4 { - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <13>; qcom,speed-bin = <0xf2>; @@ -871,13 +700,196 @@ }; }; + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + qcom,gpu-pwrlevels-5 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <14>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { From 5c8cb8774ddcc5ed96fc2a52bf75e19a0c323f36 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 17 Jul 2024 01:29:53 -0700 Subject: [PATCH 062/113] Revert "ARM: dts: msm: Use the speed bin fuse to determine sun v2 powerlevels" This reverts commit 243ac95d778d23d6e5d46200cfd4d58cf1eb4ad3. Change-Id: Icb9ba0692ee9c7e6812475ba731db30ebcdc75c2 Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 547 +--------------------------------- 1 file changed, 2 insertions(+), 545 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index df211154..cd161ec7 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -25,16 +25,12 @@ compatible = "qcom,gpu-pwrlevels-bins"; - /* - * The bins need to match based on speed bin first and then SKU. - * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. - */ qcom,gpu-pwrlevels-0 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <10>; - qcom,speed-bin = <0xbe>; + qcom,sku-codes = ; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -179,7 +175,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,speed-bin = <0xdd>; + qcom,sku-codes = ; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { @@ -349,545 +345,6 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - - qcom,gpu-pwrlevels-3 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <13>; - qcom,speed-bin = <0xf2>; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - - qcom,gpu-pwrlevels-4 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <13>; - qcom,sku-codes = ; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - - qcom,gpu-pwrlevels-5 { - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; From 2bb9ffca03d14664659f98d16989ebb14b4c4754 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 17 Jul 2024 01:30:06 -0700 Subject: [PATCH 063/113] Revert "ARM: dts: msm: Update ACD values for Sun v2 GPU" This reverts commit 7f2973e909333304c66ee8db3484c75abbaa0ab6. Change-Id: I2c495f62d3fc64a0b562902d7feafd10c3ccecb6 Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index cd161ec7..3418c791 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -5,17 +5,19 @@ /* ACD Control register values */ #define ACD_LEVEL_TURBO_L4 0x88295ffd -#define ACD_LEVEL_TURBO_L3 0x88295ffd -#define ACD_LEVEL_TURBO_L1 0xa8295ffd -#define ACD_LEVEL_NOM_L1 0x882a5ffd -#define ACD_LEVEL_NOM 0x882a5ffd -#define ACD_LEVEL_SVS_L2 0x882a5ffd -#define ACD_LEVEL_SVS_L1 0xa82a5ffd -#define ACD_LEVEL_SVS_L0 0x882c5ffd +#define ACD_LEVEL_TURBO_L3 0x882a5ffd +#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0x882b5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS_L0 0x882d5ffd #define ACD_LEVEL_SVS 0xa82e5ffd -#define ACD_LEVEL_LOW_SVS_L1 0xc02e5ffd -#define ACD_LEVEL_LOW_SVS 0xc02e5ffd -#define ACD_LEVEL_LOW_SVS_D0 0xc8285ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd +#define ACD_LEVEL_LOW_SVS 0xe02d5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd +#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd &msm_gpu { /* Power levels */ @@ -145,6 +147,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -156,6 +160,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -316,6 +322,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -327,6 +335,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -513,6 +523,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -524,6 +536,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D3 */ From 956a4269fcd748bfd69cccb4c2a25b6e75006381 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 17 Jul 2024 01:30:18 -0700 Subject: [PATCH 064/113] Revert "ARM: dts: msm: Update Sun V2 GPU frequencies" This reverts commit 154f54c2c999638fe6852cb72ec779111d59ce42. Change-Id: I1467766328bdd388756d9a2f953b6ad08d72c8a7 Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 72 ++++++++++++++--------------------- 1 file changed, 29 insertions(+), 43 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 3418c791..7a70ac8d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -4,7 +4,6 @@ */ /* ACD Control register values */ -#define ACD_LEVEL_TURBO_L4 0x88295ffd #define ACD_LEVEL_TURBO_L3 0x882a5ffd #define ACD_LEVEL_TURBO_L1 0x882a5ffd #define ACD_LEVEL_NOM_L1 0x882b5ffd @@ -355,26 +354,13 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <14>; + qcom,initial-pwrlevel = <13>; qcom,sku-codes = ; - /* TURBO_L4 */ + /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1200000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1100000000>; + qcom,gpu-freq = <1150000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -385,8 +371,8 @@ }; /* TURBO_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -398,8 +384,8 @@ }; /* NOM_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -411,8 +397,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -424,8 +410,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -437,8 +423,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -450,8 +436,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -463,8 +449,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -476,8 +462,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -489,8 +475,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -502,8 +488,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -515,8 +501,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -528,8 +514,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -541,8 +527,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@14 { - reg = <14>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <160000000>; qcom,level = ; From be3a6ce74a87f49abae5edf8f50d4e7e2373fcaf Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Thu, 11 Jul 2024 10:59:34 -0600 Subject: [PATCH 065/113] ARM: dts: msm: Set initial Sun V2 GPU freq to 222Mhz Start the GPU at a slightly higher frequency than the lowest available frequency on Sun V2 devices. Change-Id: I212c07af5de4c665ba2ff836c97f2ba1381d8fb8 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index da69ba0d..7ba3873c 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <10>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0xbe>; /* NOM */ @@ -178,7 +178,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,speed-bin = <0xdd>; /* TURBO_L1 */ @@ -349,7 +349,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,speed-bin = <0xe8>; /* TURBO_L3 */ @@ -520,7 +520,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; @@ -692,7 +692,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xf2>; /* TURBO_L3 */ @@ -876,7 +876,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <14>; + qcom,initial-pwrlevel = <13>; qcom,sku-codes = ; From 462e027ac179b916559ba15cf39f66462e50b046 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Fri, 12 Jul 2024 10:19:29 -0600 Subject: [PATCH 066/113] ARM: dts: msm: Update Sun GPU max DDR vote at SVS_L0 and SVS Update 607/660Mhz GPU max DDR limits for Sun V1 and V2. Change-Id: I94e3047155c3c1ed1c078090f7ac165c10317099 Signed-off-by: Carter Cooper --- gpu/sun-gpu-pwrlevels.dtsi | 8 ++++---- gpu/sun-v2-gpu-pwrlevels.dtsi | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 5308184d..58b57d26 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -96,7 +96,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -109,7 +109,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -298,7 +298,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -311,7 +311,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index da69ba0d..42852558 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -83,7 +83,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -96,7 +96,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -254,7 +254,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -267,7 +267,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -425,7 +425,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -438,7 +438,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -597,7 +597,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -610,7 +610,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -781,7 +781,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -794,7 +794,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -979,7 +979,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; @@ -992,7 +992,7 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <7>; + qcom,bus-max = <8>; qcom,acd-level = ; }; From 0d7213a179e2591b4b7a39ecbebafdb0ae55777c Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 8 Jul 2024 11:30:43 -0700 Subject: [PATCH 067/113] ARM: dts: msm: Add more SKUs to the Sun v2 powerlevels Add the AA SKU to the Sun v2 powerlevels so that it is recognized and selects the appropriate powerlevel table. Change-Id: I5bb706e3477efa390a8b40d24f85daabe111a0b8 Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index c299542b..da69ba0d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -521,7 +521,8 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { From bff4b4e7a30b895fcc7bf1501e7f96eaee3b0a2a Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Thu, 11 Jul 2024 10:59:34 -0600 Subject: [PATCH 068/113] ARM: dts: msm: Set initial Sun V2 GPU freq to 222Mhz Start the GPU at a slightly higher frequency than the lowest available frequency on Sun V2 devices. Change-Id: I212c07af5de4c665ba2ff836c97f2ba1381d8fb8 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index da69ba0d..7ba3873c 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <10>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0xbe>; /* NOM */ @@ -178,7 +178,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,speed-bin = <0xdd>; /* TURBO_L1 */ @@ -349,7 +349,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,speed-bin = <0xe8>; /* TURBO_L3 */ @@ -520,7 +520,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; @@ -692,7 +692,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xf2>; /* TURBO_L3 */ @@ -876,7 +876,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <14>; + qcom,initial-pwrlevel = <13>; qcom,sku-codes = ; From 8c1b2e5dea8ea07fed58d05b8946ea22cd134ec2 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Tue, 11 Jun 2024 10:56:38 -0600 Subject: [PATCH 069/113] ARM: dts: msm: Update Sun V2 GPU bus level for LOW_SVS_D2 powerlevel Lower the GPU bus range for 222Mhz powerlevel for Sun V2 devices. Change-Id: I09b5cc3019751c8dfa67d1a8fd53f6d122404fdb Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 48 +++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index c299542b..bd0f302e 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -157,9 +157,9 @@ qcom,gpu-freq = <222000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; /* Low_SVS_D3 */ @@ -168,9 +168,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -328,9 +328,9 @@ qcom,gpu-freq = <222000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; /* Low_SVS_D3 */ @@ -339,9 +339,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -499,9 +499,9 @@ qcom,gpu-freq = <222000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; /* Low_SVS_D3 */ @@ -510,9 +510,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -670,9 +670,9 @@ qcom,gpu-freq = <222000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; /* Low_SVS_D3 */ @@ -681,9 +681,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -854,9 +854,9 @@ qcom,gpu-freq = <222000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; /* Low_SVS_D3 */ @@ -865,9 +865,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; @@ -1052,9 +1052,9 @@ qcom,gpu-freq = <222000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; /* Low_SVS_D3 */ @@ -1063,9 +1063,9 @@ qcom,gpu-freq = <160000000>; qcom,level = ; - qcom,bus-freq = <3>; + qcom,bus-freq = <2>; qcom,bus-min = <2>; - qcom,bus-max = <3>; + qcom,bus-max = <2>; }; }; }; From 3beda34470626be78e2cc29bcdac42bf647d394a Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 31 Jul 2024 14:23:05 -0700 Subject: [PATCH 070/113] Revert "ARM: dts: msm: Set initial Sun V2 GPU freq to 222Mhz" This reverts commit bff4b4e7a30b895fcc7bf1501e7f96eaee3b0a2a. Change-Id: Id7cbf89788a32173572790e7ee3ede0e44e3956b Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 7ba3873c..da69ba0d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0xbe>; /* NOM */ @@ -178,7 +178,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xdd>; /* TURBO_L1 */ @@ -349,7 +349,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xe8>; /* TURBO_L3 */ @@ -520,7 +520,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,sku-codes = ; @@ -692,7 +692,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <13>; qcom,speed-bin = <0xf2>; /* TURBO_L3 */ @@ -876,7 +876,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; From 72d5c11a959ea9c24354058bf3b406029806a939 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 31 Jul 2024 14:23:17 -0700 Subject: [PATCH 071/113] Revert "ARM: dts: msm: Add more SKUs to the Sun v2 powerlevels" This reverts commit 0d7213a179e2591b4b7a39ecbebafdb0ae55777c. Change-Id: If03cbdb8cb6d79043685bd0c3efad3416b8a256a Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index da69ba0d..c299542b 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -521,8 +521,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { From bb0a96df5dc2fba14328feb3084bea4f5f6d6824 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 8 Jul 2024 11:30:43 -0700 Subject: [PATCH 072/113] ARM: dts: msm: Add more SKUs to the Sun v2 powerlevels Add the AA SKU to the Sun v2 powerlevels so that it is recognized and selects the appropriate powerlevel table. Change-Id: I319f9ba739a83dbb77b3cbaed3b8712de6ff407f Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index c299542b..da69ba0d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -521,7 +521,8 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { From 4a82759d8ee3b72f87cbfde773895c971b1e2827 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Thu, 11 Jul 2024 10:59:34 -0600 Subject: [PATCH 073/113] ARM: dts: msm: Set initial Sun V2 GPU freq to 222Mhz Start the GPU at a slightly higher frequency than the lowest available frequency on Sun V2 devices. Change-Id: I379fa4d7223486b5636933644e2fda6cbc20443a Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index da69ba0d..7ba3873c 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <10>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0xbe>; /* NOM */ @@ -178,7 +178,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,speed-bin = <0xdd>; /* TURBO_L1 */ @@ -349,7 +349,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,speed-bin = <0xe8>; /* TURBO_L3 */ @@ -520,7 +520,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; @@ -692,7 +692,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xf2>; /* TURBO_L3 */ @@ -876,7 +876,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <14>; + qcom,initial-pwrlevel = <13>; qcom,sku-codes = ; From 4d9ebbc72b953d40cc61f170fe01336d65eddf59 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Thu, 15 Aug 2024 19:44:31 -0700 Subject: [PATCH 074/113] Revert "ARM: dts: msm: Set initial Sun V2 GPU freq to 222Mhz" This reverts commit 4a82759d8ee3b72f87cbfde773895c971b1e2827. Change-Id: Ifd4fc34dbe8d3c9b2ce79384e3323a950b41eb3e Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 7ba3873c..da69ba0d 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0xbe>; /* NOM */ @@ -178,7 +178,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xdd>; /* TURBO_L1 */ @@ -349,7 +349,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xe8>; /* TURBO_L3 */ @@ -520,7 +520,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,sku-codes = ; @@ -692,7 +692,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <12>; + qcom,initial-pwrlevel = <13>; qcom,speed-bin = <0xf2>; /* TURBO_L3 */ @@ -876,7 +876,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; From 0a9efa49095240f5d2c5ef81c471a0a2cb908cc1 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Thu, 15 Aug 2024 19:44:42 -0700 Subject: [PATCH 075/113] Revert "ARM: dts: msm: Add more SKUs to the Sun v2 powerlevels" This reverts commit bb0a96df5dc2fba14328feb3084bea4f5f6d6824. Change-Id: Ib7af7f73e512c63cbcb35082c57a9c1cd9360828 Signed-off-by: Linux Image Build Automation --- gpu/sun-v2-gpu-pwrlevels.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index da69ba0d..c299542b 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -521,8 +521,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { From aacf97b95352416ae2d1c160890c65bf473b7cf2 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Wed, 4 Sep 2024 20:58:03 +0530 Subject: [PATCH 076/113] ARM: dts: msm: Add GMU CX GenPD instance Currently, there is a race condition in GenPD framework where GPU CX GDSC can remain ON if both GMU and KGSL SMMU devices are suspending in parallel and are voting on the same power domain. Guidance from genpd team is to use a dedicated power domain for CX GDSC voting. Change-Id: Iffeb9a7f24a5e3c31a325e57b021f87f8f94c7fb Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index a3e97828..be457660 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -173,8 +173,9 @@ interrupt-names = "hfi", "gmu"; power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, <&gxclkctl GX_CLKCTL_GX_GDSC>; - power-domain-names = "cx", "gx"; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From 13196ae45ef77e88b44a2f2665f4f69a53462bd5 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Sun, 29 Sep 2024 20:26:42 -0600 Subject: [PATCH 077/113] ARM: dts: msm: Add Turbo_L1 support to Sun V2 GPU freq plan Ensure the Sun V2 GPU Turbo_L1 frequency is available on AA and AB parts. Change-Id: I45f6b804a81211584efe4fcb06e4c7b3dc848263 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 122 +++++++++++++++++++++------------- 1 file changed, 74 insertions(+), 48 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 63207145..b2fe924a 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -349,7 +349,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,speed-bin = <0xe8>; /* TURBO_L3 */ @@ -365,9 +365,22 @@ qcom,acd-level = ; }; - /* NOM_L1 */ + /* TURBO_L1 */ qcom,gpu-pwrlevel@1 { reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -379,8 +392,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -392,8 +405,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -405,8 +418,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -418,8 +431,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -431,8 +444,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -444,8 +457,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -457,8 +470,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -470,8 +483,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -483,8 +496,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -494,8 +507,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -505,8 +518,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <160000000>; qcom,level = ; @@ -520,7 +533,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <11>; + qcom,initial-pwrlevel = <12>; qcom,sku-codes = ; @@ -537,9 +550,22 @@ qcom,acd-level = ; }; - /* NOM_L1 */ + /* TURBO_L1 */ qcom,gpu-pwrlevel@1 { reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -551,8 +577,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -564,8 +590,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -577,8 +603,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -590,8 +616,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -603,8 +629,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -616,8 +642,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -629,8 +655,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -642,8 +668,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -655,8 +681,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -666,8 +692,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -677,8 +703,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <160000000>; qcom,level = ; From 3e5e46ddf73adf6b6cda5327c82464a9e44edeac Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Wed, 4 Sep 2024 20:58:03 +0530 Subject: [PATCH 078/113] ARM: dts: msm: Add GMU CX GenPD instance Currently, there is a race condition in GenPD framework where GPU CX GDSC can remain ON if both GMU and KGSL SMMU devices are suspending in parallel and are voting on the same power domain. Use a dedicated power domain for CX GDSC voting as per latest recommendation. Change-Id: Iffeb9a7f24a5e3c31a325e57b021f87f8f94c7fb Signed-off-by: Kamal Agrawal --- bindings/adreno.txt | 5 +++-- gpu/sun-gpu.dtsi | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/adreno.txt b/bindings/adreno.txt index dd426a95..6bc52486 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -80,8 +80,9 @@ Power Domains: - power-domains: List of PM domain specifiers that reference each power-domain used by the GPU - power-domain-names: List of names that represent each of the specifiers in the - 'power-domains' property. Includes 'gpu_cx' and 'gpu_gx' which - represent the power-domains for CX and GX GDSC, respectively. + 'power-domains' property. Includes 'cx', 'gx' and 'gmu_cx' + which represent the power-domains for CX GDSC, GX GDSC and + GMU CX GDSC respectively. IOMMU Data: - iommu: Phandle for the KGSL IOMMU device node diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index a3e97828..be457660 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -173,8 +173,9 @@ interrupt-names = "hfi", "gmu"; power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, <&gxclkctl GX_CLKCTL_GX_GDSC>; - power-domain-names = "cx", "gx"; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From 934446a6ace7e3abcaf69070f037096cac677407 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Mon, 26 Aug 2024 17:50:50 +0530 Subject: [PATCH 079/113] ARM: dts: msm: Add support for Tuna GPU Add the devicetree files for the GPU on Tuna devices. Change-Id: I3d651d6e665c2fe40dc4e7bced2ea6bd9dbdd185 Signed-off-by: SIVA MULLATI --- Kbuild | 4 + bindings/adreno.txt | 3 + gpu/tuna-gpu-pwrlevels.dtsi | 115 ++++++++++++++++++++++++ gpu/tuna-gpu.dts | 25 ++++++ gpu/tuna-gpu.dtsi | 173 ++++++++++++++++++++++++++++++++++++ 5 files changed, 320 insertions(+) create mode 100644 gpu/tuna-gpu-pwrlevels.dtsi create mode 100644 gpu/tuna-gpu.dts create mode 100644 gpu/tuna-gpu.dtsi diff --git a/Kbuild b/Kbuild index da849afb..eef19472 100644 --- a/Kbuild +++ b/Kbuild @@ -8,6 +8,10 @@ dtbo-y += gpu/sun-gpu.dtbo \ gpu/sun-v2-gpu.dtbo endif +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += gpu/tuna-gpu.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/bindings/adreno.txt b/bindings/adreno.txt index dd426a95..caaaf7c5 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -16,6 +16,7 @@ Required properties: Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target. Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target. Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target. + Must include "qcom,adreno-gpu-gen8-6-0" for Tuna target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. @@ -183,6 +184,8 @@ Optional Properties: 1: UBWC 1.0 2: UBWC 2.0 3: UBWC 3.0 + 4: UBWC 4.0 + 5: UBWC 5.0 Based on the ubwc mode, program the appropriate bit into certain protected registers and also pass to the user as a property. diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..278d4fca --- /dev/null +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&msm_gpu { + /* Power levels */ + qcom,initial-pwrlevel = <8>; + + qcom,gpu-pwrlevels { + compatible="qcom,gpu-pwrlevels"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <9>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <4>; + qcom,bus-max = <8>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <7>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; +}; diff --git a/gpu/tuna-gpu.dts b/gpu/tuna-gpu.dts new file mode 100644 index 00000000..0c480c2d --- /dev/null +++ b/gpu/tuna-gpu.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "tuna-gpu.dtsi" +#include "tuna-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna"; + compatible = "qcom,tuna"; + qcom,msm-id = <0x28f 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi new file mode 100644 index 00000000..0034b508 --- /dev/null +++ b/gpu/tuna-gpu.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +/* External feature codes */ +#define FC_UNKNOWN 0x0 + +/* Pcodes */ +#define PCODE_UNKNOWN 0 + +#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen8-6-0", "qcom,kgsl-3d0"; + status = "ok"; + reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, + <0x3d61000 0x3000>, <0x3d9e000 0x2000>, + <0x10900000 0x80000>, <0x10048000 0x8000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", + "qdss_gfx", "qdss_etr", "qdss_tmc"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb"; + + qcom,gpu-model = "Adreno825"; + + qcom,chipid = <0x44030000>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <5>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* NOM index=8 */ + , /* TURBO index=9 */ + , /* TURBO_L1 index=10 */ + ; /* TURBO_L3 index=11 */ + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x3da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d37000 { + compatible = "qcom,gen8-gmu"; + + reg = <0x3d37000 0x68000>, + <0x3d40000 0x10000>; + + reg-names = "gmu", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gx_clkctl_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk"; + + qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <650000000 RPMH_REGULATOR_LEVEL_SVS>; + qcom,gmu-perf-ddr-bw = ; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + + qcom,ipc-core = <0x00400000 0x140000>; + + qcom,qmp = <&aoss_qmp>; + }; +}; From f13aad44f17f63066631641c73e37e87708047bc Mon Sep 17 00:00:00 2001 From: "V S Ganga VaraPrasad (VARA) Adabala" Date: Sat, 26 Oct 2024 21:56:34 +0530 Subject: [PATCH 080/113] Revert "ARM: dts: msm: Add GMU CX GenPD instance" This reverts commit aacf97b95352416ae2d1c160890c65bf473b7cf2. Change-Id: I3337457b06ba37da2cfa902e04de367195a4836a Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala --- gpu/sun-gpu.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index be457660..a3e97828 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -173,9 +173,8 @@ interrupt-names = "hfi", "gmu"; power-domains = <&gpucc GPU_CC_CX_GDSC>, - <&gpucc GPU_CC_CX_GMU_GDSC>, <&gxclkctl GX_CLKCTL_GX_GDSC>; - power-domain-names = "cx", "gmu_cx", "gx"; + power-domain-names = "cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From 27a82907466758190d32e673b24a7f4d6410f757 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Wed, 4 Sep 2024 20:58:03 +0530 Subject: [PATCH 081/113] ARM: dts: msm: Add GMU CX GenPD instance Currently, there is a race condition in GenPD framework where GPU CX GDSC can remain ON if both GMU and KGSL SMMU devices are suspending in parallel and are voting on the same power domain. Use a dedicated power domain for CX GDSC voting as per latest recommendation. Change-Id: Iffeb9a7f24a5e3c31a425e57b021f87f8f94c7fb Signed-off-by: Kamal Agrawal --- bindings/adreno.txt | 5 +++-- gpu/sun-gpu.dtsi | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/adreno.txt b/bindings/adreno.txt index dd426a95..6bc52486 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -80,8 +80,9 @@ Power Domains: - power-domains: List of PM domain specifiers that reference each power-domain used by the GPU - power-domain-names: List of names that represent each of the specifiers in the - 'power-domains' property. Includes 'gpu_cx' and 'gpu_gx' which - represent the power-domains for CX and GX GDSC, respectively. + 'power-domains' property. Includes 'cx', 'gx' and 'gmu_cx' + which represent the power-domains for CX GDSC, GX GDSC and + GMU CX GDSC respectively. IOMMU Data: - iommu: Phandle for the KGSL IOMMU device node diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index a3e97828..be457660 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -173,8 +173,9 @@ interrupt-names = "hfi", "gmu"; power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, <&gxclkctl GX_CLKCTL_GX_GDSC>; - power-domain-names = "cx", "gx"; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From f2f44ab4ad57fa4523ea6a349444403dfda96efa Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Mon, 26 Aug 2024 17:50:50 +0530 Subject: [PATCH 082/113] ARM: dts: msm: Add support for Tuna GPU Add the devicetree files for the GPU on Tuna devices. Change-Id: I3d651d6e665c2fe40dc4e7bced2ea6bd9dbdd185 Signed-off-by: SIVA MULLATI (cherry picked from commit 934446a6ace7e3abcaf69070f037096cac677407) --- Kbuild | 4 + bindings/adreno.txt | 3 + gpu/tuna-gpu-pwrlevels.dtsi | 115 ++++++++++++++++++++++++ gpu/tuna-gpu.dts | 25 ++++++ gpu/tuna-gpu.dtsi | 173 ++++++++++++++++++++++++++++++++++++ 5 files changed, 320 insertions(+) create mode 100644 gpu/tuna-gpu-pwrlevels.dtsi create mode 100644 gpu/tuna-gpu.dts create mode 100644 gpu/tuna-gpu.dtsi diff --git a/Kbuild b/Kbuild index da849afb..eef19472 100644 --- a/Kbuild +++ b/Kbuild @@ -8,6 +8,10 @@ dtbo-y += gpu/sun-gpu.dtbo \ gpu/sun-v2-gpu.dtbo endif +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += gpu/tuna-gpu.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/bindings/adreno.txt b/bindings/adreno.txt index 6bc52486..0f5c0311 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -16,6 +16,7 @@ Required properties: Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target. Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target. Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target. + Must include "qcom,adreno-gpu-gen8-6-0" for Tuna target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. @@ -184,6 +185,8 @@ Optional Properties: 1: UBWC 1.0 2: UBWC 2.0 3: UBWC 3.0 + 4: UBWC 4.0 + 5: UBWC 5.0 Based on the ubwc mode, program the appropriate bit into certain protected registers and also pass to the user as a property. diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..278d4fca --- /dev/null +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&msm_gpu { + /* Power levels */ + qcom,initial-pwrlevel = <8>; + + qcom,gpu-pwrlevels { + compatible="qcom,gpu-pwrlevels"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <9>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <4>; + qcom,bus-max = <8>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <7>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; +}; diff --git a/gpu/tuna-gpu.dts b/gpu/tuna-gpu.dts new file mode 100644 index 00000000..0c480c2d --- /dev/null +++ b/gpu/tuna-gpu.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "tuna-gpu.dtsi" +#include "tuna-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna"; + compatible = "qcom,tuna"; + qcom,msm-id = <0x28f 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi new file mode 100644 index 00000000..0034b508 --- /dev/null +++ b/gpu/tuna-gpu.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +/* External feature codes */ +#define FC_UNKNOWN 0x0 + +/* Pcodes */ +#define PCODE_UNKNOWN 0 + +#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen8-6-0", "qcom,kgsl-3d0"; + status = "ok"; + reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, + <0x3d61000 0x3000>, <0x3d9e000 0x2000>, + <0x10900000 0x80000>, <0x10048000 0x8000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", + "qdss_gfx", "qdss_etr", "qdss_tmc"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb"; + + qcom,gpu-model = "Adreno825"; + + qcom,chipid = <0x44030000>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <5>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* NOM index=8 */ + , /* TURBO index=9 */ + , /* TURBO_L1 index=10 */ + ; /* TURBO_L3 index=11 */ + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x3da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d37000 { + compatible = "qcom,gen8-gmu"; + + reg = <0x3d37000 0x68000>, + <0x3d40000 0x10000>; + + reg-names = "gmu", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gx_clkctl_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk"; + + qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <650000000 RPMH_REGULATOR_LEVEL_SVS>; + qcom,gmu-perf-ddr-bw = ; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + + qcom,ipc-core = <0x00400000 0x140000>; + + qcom,qmp = <&aoss_qmp>; + }; +}; From 8e45dbe4a718297ef45d80463b92e2e6695cc8a9 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Tue, 29 Oct 2024 14:48:25 +0530 Subject: [PATCH 083/113] ARM: dts: msm: Update Tuna GPU Enable cx_host_irq, genPD and update bus frequency for Tuna GPU. Change-Id: I192fccfe65191ea73d4be4cdca245d65830acc0e Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu-pwrlevels.dtsi | 32 ++++++++++++++++---------------- gpu/tuna-gpu.dtsi | 24 ++++++++++++++---------- 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 278d4fca..8294ea31 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -19,9 +19,9 @@ qcom,gpu-freq = <1050000000>; qcom,level = ; - qcom,bus-freq = <9>; - qcom,bus-min = <9>; - qcom,bus-max = <9>; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; }; /* Turbo */ @@ -30,9 +30,9 @@ qcom,gpu-freq = <937000000>; qcom,level = ; - qcom,bus-freq = <9>; - qcom,bus-min = <8>; - qcom,bus-max = <9>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; }; /* Nom_L1 */ @@ -41,7 +41,7 @@ qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <8>; + qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; }; @@ -52,9 +52,9 @@ qcom,gpu-freq = <763000000>; qcom,level = ; - qcom,bus-freq = <7>; - qcom,bus-min = <6>; - qcom,bus-max = <8>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; }; /* SVS_L2 */ @@ -63,9 +63,9 @@ qcom,gpu-freq = <688000000>; qcom,level = ; - qcom,bus-freq = <7>; - qcom,bus-min = <5>; - qcom,bus-max = <8>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; }; /* SVS_L1 */ @@ -74,9 +74,9 @@ qcom,gpu-freq = <644000000>; qcom,level = ; - qcom,bus-freq = <7>; + qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <8>; + qcom,bus-max = <7>; }; /* SVS */ @@ -87,7 +87,7 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; - qcom,bus-max = <7>; + qcom,bus-max = <6>; }; /* Low_SVS */ diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index 0034b508..c56c55ff 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -23,11 +23,15 @@ reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq", "cx_host_irq"; - clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; - clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb"; + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&aoss_qmp QDSS_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gpu_cc_ahb", + "apb_pclk"; qcom,gpu-model = "Adreno825"; @@ -56,7 +60,7 @@ , /* NOM index=8 */ , /* TURBO index=9 */ , /* TURBO_L1 index=10 */ - ; /* TURBO_L3 index=11 */ + ; /* TURBO_L2 index=11 */ zap-shader { memory-region = <&gpu_microcode_mem>; @@ -111,7 +115,7 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x3da0000 0x40000>; - vddcx-supply = <&gpu_cc_cx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -144,10 +148,10 @@ <0 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - regulator-names = "vddcx", "vdd"; - - vddcx-supply = <&gpu_cc_cx_gdsc>; - vdd-supply = <&gx_clkctl_gx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From 2dbee8500121b254fcd5af3ab889bb4ebfb635e5 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Tue, 29 Oct 2024 14:48:25 +0530 Subject: [PATCH 084/113] ARM: dts: msm: Update Tuna GPU Enable cx_host_irq, genPD and update bus frequency for Tuna GPU. Change-Id: I192fccfe65191ea73d4be4cdca245d65830acc0e Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu-pwrlevels.dtsi | 32 ++++++++++++++++---------------- gpu/tuna-gpu.dtsi | 24 ++++++++++++++---------- 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 278d4fca..8294ea31 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -19,9 +19,9 @@ qcom,gpu-freq = <1050000000>; qcom,level = ; - qcom,bus-freq = <9>; - qcom,bus-min = <9>; - qcom,bus-max = <9>; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; }; /* Turbo */ @@ -30,9 +30,9 @@ qcom,gpu-freq = <937000000>; qcom,level = ; - qcom,bus-freq = <9>; - qcom,bus-min = <8>; - qcom,bus-max = <9>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; }; /* Nom_L1 */ @@ -41,7 +41,7 @@ qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <8>; + qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; }; @@ -52,9 +52,9 @@ qcom,gpu-freq = <763000000>; qcom,level = ; - qcom,bus-freq = <7>; - qcom,bus-min = <6>; - qcom,bus-max = <8>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; }; /* SVS_L2 */ @@ -63,9 +63,9 @@ qcom,gpu-freq = <688000000>; qcom,level = ; - qcom,bus-freq = <7>; - qcom,bus-min = <5>; - qcom,bus-max = <8>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; }; /* SVS_L1 */ @@ -74,9 +74,9 @@ qcom,gpu-freq = <644000000>; qcom,level = ; - qcom,bus-freq = <7>; + qcom,bus-freq = <6>; qcom,bus-min = <4>; - qcom,bus-max = <8>; + qcom,bus-max = <7>; }; /* SVS */ @@ -87,7 +87,7 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; - qcom,bus-max = <7>; + qcom,bus-max = <6>; }; /* Low_SVS */ diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index 0034b508..c56c55ff 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -23,11 +23,15 @@ reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq", "cx_host_irq"; - clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; - clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb"; + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&aoss_qmp QDSS_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gpu_cc_ahb", + "apb_pclk"; qcom,gpu-model = "Adreno825"; @@ -56,7 +60,7 @@ , /* NOM index=8 */ , /* TURBO index=9 */ , /* TURBO_L1 index=10 */ - ; /* TURBO_L3 index=11 */ + ; /* TURBO_L2 index=11 */ zap-shader { memory-region = <&gpu_microcode_mem>; @@ -111,7 +115,7 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x3da0000 0x40000>; - vddcx-supply = <&gpu_cc_cx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -144,10 +148,10 @@ <0 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - regulator-names = "vddcx", "vdd"; - - vddcx-supply = <&gpu_cc_cx_gdsc>; - vdd-supply = <&gx_clkctl_gx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From b75b1742d60b9a8b54f4c0e4e97dcdd97491e7d9 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 11 Dec 2024 18:21:01 +0530 Subject: [PATCH 085/113] ARM: dts: msm: Add tzone-names for Tuna GPU Add GPU tzone-names to get the GPU temperature on Tuna gpu. Change-Id: I71ab003259484ea0fa7f9c9613967909bef6c6c3 Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index c56c55ff..80807520 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -41,6 +41,9 @@ qcom,ubwc-mode = <5>; + qcom,tzone-names = "gpu-0", "gpu-1", "gpu-2", "gpu-3", + "gpu-4", "gpu-5"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path"; From 1f4df4368b9112b8ad63e20fcbe248a3c8366b14 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Fri, 1 Nov 2024 14:35:44 +0530 Subject: [PATCH 086/113] ARM: dts: msm: Add dt support for TunaP gpu Add the necessary initial support for TunaP variant. Change-Id: Iff04d6992010da8a496a53727378fc5e1e5cd88c Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/tuna-gpu.dts b/gpu/tuna-gpu.dts index 0c480c2d..2f29cdef 100644 --- a/gpu/tuna-gpu.dts +++ b/gpu/tuna-gpu.dts @@ -19,7 +19,7 @@ / { model = "Qualcomm Technologies, Inc. tuna"; - compatible = "qcom,tuna"; - qcom,msm-id = <0x28f 0x10000>; + compatible = "qcom,tuna", "qcom,tunap"; + qcom,msm-id = <0x28f 0x10000>, <0x2b6 0x10000>; qcom,board-id = <0 0>; }; From af0e7a0660bfbe4c218711f0776c9e7b1f45fcc6 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 13 Nov 2024 20:06:34 +0530 Subject: [PATCH 087/113] ARM: dts: msm: Add support for Tuna7 GPU Add initial support for Tuna7 GPU in the devicetree. Change-Id: I66ac7382ce0dfc10291a2318e0da3d9880c24790 Signed-off-by: SIVA MULLATI --- Kbuild | 3 +- gpu/tuna-gpu-pwrlevels.dtsi | 390 ++++++++++++++++++++++++++++-------- gpu/tuna-gpu.dtsi | 3 + gpu/tuna7-gpu.dts | 30 +++ gpu/tuna7-gpu.dtsi | 10 + 5 files changed, 352 insertions(+), 84 deletions(-) create mode 100644 gpu/tuna7-gpu.dts create mode 100644 gpu/tuna7-gpu.dtsi diff --git a/Kbuild b/Kbuild index eef19472..d56aed40 100644 --- a/Kbuild +++ b/Kbuild @@ -9,7 +9,8 @@ dtbo-y += gpu/sun-gpu.dtbo \ endif ifeq ($(CONFIG_ARCH_TUNA), y) -dtbo-y += gpu/tuna-gpu.dtbo +dtbo-y += gpu/tuna-gpu.dtbo \ + gpu/tuna7-gpu.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 8294ea31..5d8edc86 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -5,111 +5,335 @@ &msm_gpu { /* Power levels */ - qcom,initial-pwrlevel = <8>; - - qcom,gpu-pwrlevels { - compatible="qcom,gpu-pwrlevels"; - + qcom,gpu-pwrlevel-bins { #address-cells = <1>; #size-cells = <0>; - /* Turbo_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; + compatible = "qcom,gpu-pwrlevels-bins"; - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; + /* + * The bins need to match based on speed bin first and then SKU. + * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. + */ + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; - /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <937000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq = <10>; - qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0xd8>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1025000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; - /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <873000000>; - qcom,level = ; + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq = <9>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0xf2>; - /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <763000000>; - qcom,level = ; + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <688000000>; - qcom,level = ; + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <644000000>; - qcom,level = ; + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <510000000>; - qcom,level = ; + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <362000000>; - qcom,level = ; + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; - qcom,bus-freq = <3>; - qcom,bus-min = <1>; - qcom,bus-max = <3>; - }; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <264000000>; - qcom,level = ; + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; - qcom,bus-freq = <1>; - qcom,bus-min = <1>; - qcom,bus-max = <3>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; }; }; diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index c56c55ff..2adffa7d 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -62,6 +62,9 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L2 index=11 */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; diff --git a/gpu/tuna7-gpu.dts b/gpu/tuna7-gpu.dts new file mode 100644 index 00000000..5e5ce5e9 --- /dev/null +++ b/gpu/tuna7-gpu.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "tuna-gpu.dtsi" +#include "tuna-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna7 SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <0x2a9 0x10000>; + qcom,board-id = <0 0>; +}; + +&msm_gpu { + /delete-property/qcom,gpu-model; + qcom,gpu-model = "Adreno822"; +}; diff --git a/gpu/tuna7-gpu.dtsi b/gpu/tuna7-gpu.dtsi new file mode 100644 index 00000000..2a286fac --- /dev/null +++ b/gpu/tuna7-gpu.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-gpu.dtsi" + +&msm_gpu { + qcom,gpu-model = "Adreno822"; +}; From 45d0da9b2751511189091aad2a1558be9eaae1d2 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 8 Nov 2024 17:35:02 +0530 Subject: [PATCH 088/113] ARM: dts: msm: Add support for Kera GPU Add support for Kera GPU. Change-Id: I46ac3fd2e4a21a5b95e7f5d372e546ab2dec11ca Signed-off-by: Harshitha Sai Neelati --- Kbuild | 4 + bindings/adreno.txt | 1 + gpu/kera-gpu-pwrlevels.dtsi | 151 +++++++++++++++++++++++++++++++++ gpu/kera-gpu.dts | 25 ++++++ gpu/kera-gpu.dtsi | 165 ++++++++++++++++++++++++++++++++++++ 5 files changed, 346 insertions(+) create mode 100644 gpu/kera-gpu-pwrlevels.dtsi create mode 100644 gpu/kera-gpu.dts create mode 100644 gpu/kera-gpu.dtsi diff --git a/Kbuild b/Kbuild index eef19472..311841fd 100644 --- a/Kbuild +++ b/Kbuild @@ -12,6 +12,10 @@ ifeq ($(CONFIG_ARCH_TUNA), y) dtbo-y += gpu/tuna-gpu.dtbo endif +ifeq ($(CONFIG_ARCH_KERA), y) +dtbo-y += gpu/kera-gpu.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/bindings/adreno.txt b/bindings/adreno.txt index 0f5c0311..d2855ed0 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -16,6 +16,7 @@ Required properties: Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target. Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target. Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target. + Must include "qcom,adreno-gpu-gen7-17-0" for Kera target. Must include "qcom,adreno-gpu-gen8-6-0" for Tuna target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..bba8f52f --- /dev/null +++ b/gpu/kera-gpu-pwrlevels.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&msm_gpu { + qcom,initial-pwrlevel = <7>; + + /* Power levels */ + qcom,gpu-pwrlevels { + compatible="qcom,gpu-pwrlevels"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1075000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <975000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <9>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <8>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <796000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <724000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <645000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <515000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <3>; + qcom,bus-max-ddr7 = <6>; + + qcom,bus-freq-ddr8 = <4>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <5>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <345000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <6>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <4>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <259000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <1>; + qcom,bus-max-ddr7 = <6>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <4>; + }; + }; +}; diff --git a/gpu/kera-gpu.dts b/gpu/kera-gpu.dts new file mode 100644 index 00000000..5c8ca057 --- /dev/null +++ b/gpu/kera-gpu.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "kera-gpu.dtsi" +#include "kera-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <0x293 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi new file mode 100644 index 00000000..c1c2eb31 --- /dev/null +++ b/gpu/kera-gpu.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0"; + status = "ok"; + reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, + <0x3d61000 0x800>, <0x3d9e000 0x1000>, + <0x10048000 0x8000>, <0x10900000 0x80000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", + "cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>; + clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk"; + + qcom,gpu-model = "Adreno716"; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <4>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* NOM index=8 */ + , /* TURBO index=9 */ + ; /* TURBO_L1 index=10 */ + + qcom,bus-table-ddr8 = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* TURBO index=8 */ + , /* TURBO index=9 */ + ; /* TURBO_L1 index=10 */ + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x3da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d68000 { + compatible = "qcom,gen7-gmu"; + + reg = <0x3d68000 0x37000>, <0xb290000 0x10000>, <0x3d40000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gpu_cc_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; + + qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <550000000 RPMH_REGULATOR_LEVEL_SVS>; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + }; +}; From 32220770b5987a914411c862c84b08f5ab0e1ac5 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Mon, 9 Dec 2024 23:14:04 +0530 Subject: [PATCH 089/113] ARM: dts: msm: Add SoC ID support for KeraP gpu Add the necessary SoC ID support for KeraP variant. Change-Id: Id348e77a19835b09f7f54d3486e73e3c93530ca2 Signed-off-by: Harshitha Sai Neelati --- gpu/kera-gpu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/kera-gpu.dts b/gpu/kera-gpu.dts index 5c8ca057..f81d3e07 100644 --- a/gpu/kera-gpu.dts +++ b/gpu/kera-gpu.dts @@ -19,7 +19,7 @@ / { model = "Qualcomm Technologies, Inc. Kera SoC"; - compatible = "qcom,kera"; - qcom,msm-id = <0x293 0x10000>; + compatible = "qcom,kera", "qcom,kerap"; + qcom,msm-id = <0x293 0x10000>, <0x2ae 0x10000>; qcom,board-id = <0 0>; }; From 8231295e9b098b74c5206b73bf545c942b4f4369 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Fri, 1 Nov 2024 14:35:44 +0530 Subject: [PATCH 090/113] ARM: dts: msm: Add dt support for TunaP gpu Add the necessary initial support for TunaP variant. Change-Id: Iff04d6992010da8a496a53727378fc5e1e5cd88c Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/tuna-gpu.dts b/gpu/tuna-gpu.dts index 0c480c2d..2f29cdef 100644 --- a/gpu/tuna-gpu.dts +++ b/gpu/tuna-gpu.dts @@ -19,7 +19,7 @@ / { model = "Qualcomm Technologies, Inc. tuna"; - compatible = "qcom,tuna"; - qcom,msm-id = <0x28f 0x10000>; + compatible = "qcom,tuna", "qcom,tunap"; + qcom,msm-id = <0x28f 0x10000>, <0x2b6 0x10000>; qcom,board-id = <0 0>; }; From db0d4b3372dce48f4de8a3fbb79baca3452ecea4 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 13 Nov 2024 20:06:34 +0530 Subject: [PATCH 091/113] ARM: dts: msm: Add support for Tuna7 GPU Add initial support for Tuna7 GPU in the devicetree. Change-Id: I66ac7382ce0dfc10291a2318e0da3d9880c24790 Signed-off-by: SIVA MULLATI --- Kbuild | 3 +- gpu/tuna-gpu-pwrlevels.dtsi | 390 ++++++++++++++++++++++++++++-------- gpu/tuna-gpu.dtsi | 3 + gpu/tuna7-gpu.dts | 30 +++ gpu/tuna7-gpu.dtsi | 10 + 5 files changed, 352 insertions(+), 84 deletions(-) create mode 100644 gpu/tuna7-gpu.dts create mode 100644 gpu/tuna7-gpu.dtsi diff --git a/Kbuild b/Kbuild index eef19472..d56aed40 100644 --- a/Kbuild +++ b/Kbuild @@ -9,7 +9,8 @@ dtbo-y += gpu/sun-gpu.dtbo \ endif ifeq ($(CONFIG_ARCH_TUNA), y) -dtbo-y += gpu/tuna-gpu.dtbo +dtbo-y += gpu/tuna-gpu.dtbo \ + gpu/tuna7-gpu.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 8294ea31..5d8edc86 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -5,111 +5,335 @@ &msm_gpu { /* Power levels */ - qcom,initial-pwrlevel = <8>; - - qcom,gpu-pwrlevels { - compatible="qcom,gpu-pwrlevels"; - + qcom,gpu-pwrlevel-bins { #address-cells = <1>; #size-cells = <0>; - /* Turbo_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; + compatible = "qcom,gpu-pwrlevels-bins"; - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; + /* + * The bins need to match based on speed bin first and then SKU. + * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. + */ + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; - /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <937000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq = <10>; - qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0xd8>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1025000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; - /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <873000000>; - qcom,level = ; + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq = <9>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0xf2>; - /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <763000000>; - qcom,level = ; + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <688000000>; - qcom,level = ; + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <644000000>; - qcom,level = ; + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <510000000>; - qcom,level = ; + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <362000000>; - qcom,level = ; + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; - qcom,bus-freq = <3>; - qcom,bus-min = <1>; - qcom,bus-max = <3>; - }; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <264000000>; - qcom,level = ; + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; - qcom,bus-freq = <1>; - qcom,bus-min = <1>; - qcom,bus-max = <3>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; }; }; diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index c56c55ff..2adffa7d 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -62,6 +62,9 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L2 index=11 */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; diff --git a/gpu/tuna7-gpu.dts b/gpu/tuna7-gpu.dts new file mode 100644 index 00000000..5e5ce5e9 --- /dev/null +++ b/gpu/tuna7-gpu.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "tuna-gpu.dtsi" +#include "tuna-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna7 SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <0x2a9 0x10000>; + qcom,board-id = <0 0>; +}; + +&msm_gpu { + /delete-property/qcom,gpu-model; + qcom,gpu-model = "Adreno822"; +}; diff --git a/gpu/tuna7-gpu.dtsi b/gpu/tuna7-gpu.dtsi new file mode 100644 index 00000000..2a286fac --- /dev/null +++ b/gpu/tuna7-gpu.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-gpu.dtsi" + +&msm_gpu { + qcom,gpu-model = "Adreno822"; +}; From bc0f760601174e6bbd1c7187a98ae30ab14639ba Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 20 Dec 2024 15:38:15 +0530 Subject: [PATCH 092/113] ARM: dts: msm: Enable GenPD support for Kera GPU Enable GenPD support for Kera GPU. Change-Id: Ia9b1a99c694fc7d64f99c572d09388f82dc0a78c Signed-off-by: Harshitha Sai Neelati --- gpu/kera-gpu.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index c1c2eb31..2cec634e 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -115,7 +115,7 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x3da0000 0x40000>; - vddcx-supply = <&gpu_cc_cx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -140,10 +140,10 @@ <0 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - regulator-names = "vddcx", "vdd"; - - vddcx-supply = <&gpu_cc_cx_gdsc>; - vdd-supply = <&gpu_cc_gx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From a7ea1feb1b9d37d9a4db5322ea379e292f8d1040 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 8 Nov 2024 17:35:02 +0530 Subject: [PATCH 093/113] ARM: dts: msm: Add support for Kera GPU Add support for Kera GPU. Change-Id: I46ac3fd2e4a21a5b95e7f5d372e546ab2dec11ca Signed-off-by: Harshitha Sai Neelati --- Kbuild | 4 + bindings/adreno.txt | 1 + gpu/kera-gpu-pwrlevels.dtsi | 151 +++++++++++++++++++++++++++++++++ gpu/kera-gpu.dts | 25 ++++++ gpu/kera-gpu.dtsi | 165 ++++++++++++++++++++++++++++++++++++ 5 files changed, 346 insertions(+) create mode 100644 gpu/kera-gpu-pwrlevels.dtsi create mode 100644 gpu/kera-gpu.dts create mode 100644 gpu/kera-gpu.dtsi diff --git a/Kbuild b/Kbuild index d56aed40..dd90ced9 100644 --- a/Kbuild +++ b/Kbuild @@ -13,6 +13,10 @@ dtbo-y += gpu/tuna-gpu.dtbo \ gpu/tuna7-gpu.dtbo endif +ifeq ($(CONFIG_ARCH_KERA), y) +dtbo-y += gpu/kera-gpu.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/bindings/adreno.txt b/bindings/adreno.txt index 0f5c0311..d2855ed0 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -16,6 +16,7 @@ Required properties: Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target. Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target. Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target. + Must include "qcom,adreno-gpu-gen7-17-0" for Kera target. Must include "qcom,adreno-gpu-gen8-6-0" for Tuna target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..bba8f52f --- /dev/null +++ b/gpu/kera-gpu-pwrlevels.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&msm_gpu { + qcom,initial-pwrlevel = <7>; + + /* Power levels */ + qcom,gpu-pwrlevels { + compatible="qcom,gpu-pwrlevels"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1075000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <975000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <9>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <8>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <796000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <724000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <645000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <515000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <3>; + qcom,bus-max-ddr7 = <6>; + + qcom,bus-freq-ddr8 = <4>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <5>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <345000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <6>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <4>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <259000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <1>; + qcom,bus-max-ddr7 = <6>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <4>; + }; + }; +}; diff --git a/gpu/kera-gpu.dts b/gpu/kera-gpu.dts new file mode 100644 index 00000000..5c8ca057 --- /dev/null +++ b/gpu/kera-gpu.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "kera-gpu.dtsi" +#include "kera-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <0x293 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi new file mode 100644 index 00000000..c1c2eb31 --- /dev/null +++ b/gpu/kera-gpu.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0"; + status = "ok"; + reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, + <0x3d61000 0x800>, <0x3d9e000 0x1000>, + <0x10048000 0x8000>, <0x10900000 0x80000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", + "cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>; + clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk"; + + qcom,gpu-model = "Adreno716"; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <4>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* NOM index=8 */ + , /* TURBO index=9 */ + ; /* TURBO_L1 index=10 */ + + qcom,bus-table-ddr8 = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* TURBO index=8 */ + , /* TURBO index=9 */ + ; /* TURBO_L1 index=10 */ + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x3da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d68000 { + compatible = "qcom,gen7-gmu"; + + reg = <0x3d68000 0x37000>, <0xb290000 0x10000>, <0x3d40000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gpu_cc_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; + + qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <550000000 RPMH_REGULATOR_LEVEL_SVS>; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + }; +}; From eb671c826b8e4961dac01c9568258442808b80d3 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Mon, 9 Dec 2024 23:14:04 +0530 Subject: [PATCH 094/113] ARM: dts: msm: Add SoC ID support for KeraP gpu Add the necessary SoC ID support for KeraP variant. Change-Id: Id348e77a19835b09f7f54d3486e73e3c93530ca2 Signed-off-by: Harshitha Sai Neelati --- gpu/kera-gpu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/kera-gpu.dts b/gpu/kera-gpu.dts index 5c8ca057..f81d3e07 100644 --- a/gpu/kera-gpu.dts +++ b/gpu/kera-gpu.dts @@ -19,7 +19,7 @@ / { model = "Qualcomm Technologies, Inc. Kera SoC"; - compatible = "qcom,kera"; - qcom,msm-id = <0x293 0x10000>; + compatible = "qcom,kera", "qcom,kerap"; + qcom,msm-id = <0x293 0x10000>, <0x2ae 0x10000>; qcom,board-id = <0 0>; }; From 3fb5444e6df03d26bada3091816cdd9de1b1e0d7 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 20 Dec 2024 15:38:15 +0530 Subject: [PATCH 095/113] ARM: dts: msm: Enable GenPD support for Kera GPU Enable GenPD support for Kera GPU. Change-Id: Ia9b1a99c694fc7d64f99c572d09388f82dc0a78c Signed-off-by: Harshitha Sai Neelati --- gpu/kera-gpu.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index c1c2eb31..2cec634e 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -115,7 +115,7 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x3da0000 0x40000>; - vddcx-supply = <&gpu_cc_cx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -140,10 +140,10 @@ <0 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - regulator-names = "vddcx", "vdd"; - - vddcx-supply = <&gpu_cc_cx_gdsc>; - vdd-supply = <&gpu_cc_gx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From d69fe4603a743426896104ebf07f16f4b6c737b5 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Wed, 25 Dec 2024 15:15:58 +0530 Subject: [PATCH 096/113] ARM: dts: msm: add chipid for KERA gpu Change-Id: Ib28e8f9d1715ac6dd48c35bdcb3c4f69221d1bef --- gpu/kera-gpu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 2cec634e..60ac5105 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -25,6 +25,8 @@ qcom,gpu-model = "Adreno716"; + qcom,chipid = <0x43020100>; + qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; From f033f869e101c8830f8a81fdfd64494e6a579845 Mon Sep 17 00:00:00 2001 From: Siva Srinivas Venigalla Date: Wed, 25 Dec 2024 15:07:19 +0530 Subject: [PATCH 097/113] ARM: dts: msm: Add tzone-names for Kera GPU Add GPU tzone-names to get the GPU temperature on Kera gpu. Change-Id: Id4f45ffc3b9d34d9019fdbc4b27820c5868590ab Signed-off-by: Siva Srinivas Venigalla --- gpu/kera-gpu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 2cec634e..22834a3f 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -29,6 +29,8 @@ qcom,ubwc-mode = <4>; + qcom,tzone-names = "gpuss-0", "gpuss-1"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path"; From 980d714a763ff3da28ff7d6052727a0f746edee2 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Thu, 9 Jan 2025 13:30:44 +0530 Subject: [PATCH 098/113] ARM: dts: msm: Add the nvmem cells for gaming fuse on kera gpu Define the nvmem cells for gaming fuse support on kera gpu. Change-Id: I3e316771845e01f1bba42040084be1f735099298 Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 22834a3f..fadae3a6 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -64,6 +64,9 @@ , /* TURBO index=9 */ ; /* TURBO_L1 index=10 */ + nvmem-cells = <&gpu_gaming_bin>; + nvmem-cell-names = "gaming_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; From a1c6877f852e1d35eda0d94f774a8b7ee7955ded Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Fri, 17 Jan 2025 19:41:40 +0530 Subject: [PATCH 099/113] ARM: dts: msm: Add freq limiter interrupt and reset support for Kera Add frequency limiter interrupt and reset support for GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR for Kera gpu. Change-Id: I6145a638b9a0435dfcacbaf60859e1adbe1ee2dc Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index fadae3a6..24fea604 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -15,8 +15,11 @@ reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 286 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq"; + + resets = <&gpucc GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>; + reset-names = "freq_limiter_irq_clear"; clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>; From 31cd596f9b7ad0fff38e23eed539648b7b55afa8 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 4 Dec 2024 17:57:10 +0530 Subject: [PATCH 100/113] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. Change-Id: I5c904b148f149f094dea735ba0a975862538dad6 Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu-pwrlevels.dtsi | 163 ++++++++++++++++++++++++++++-------- 1 file changed, 127 insertions(+), 36 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 5d8edc86..9839dafb 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -3,6 +3,18 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L2 0xa02f5ffd +#define ACD_LEVEL_TURBO_L1 0xa8285ffd +#define ACD_LEVEL_TURBO 0x88295ffd +#define ACD_LEVEL_NOM_L1 0xa8295ffd +#define ACD_LEVEL_NOM 0x882a5ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0xa82a5ffd +#define ACD_LEVEL_SVS 0xa82c5ffd +#define ACD_LEVEL_LOW_SVS 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd + &msm_gpu { /* Power levels */ qcom,gpu-pwrlevel-bins { @@ -19,106 +31,137 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <8>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <873000000>; qcom,level = ; qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <763000000>; qcom,level = ; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <688000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <644000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <510000000>; qcom,level = ; qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <362000000>; qcom,level = ; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <264000000>; qcom,level = ; qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -138,6 +181,8 @@ qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ @@ -149,6 +194,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ @@ -160,6 +207,7 @@ qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + qcom,acd-level = ; }; /* Nom */ @@ -171,6 +219,8 @@ qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -182,6 +232,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -193,6 +245,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -204,6 +258,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -215,6 +271,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -226,6 +284,8 @@ qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -233,106 +293,137 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <8>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0xf2>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <873000000>; qcom,level = ; qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <763000000>; qcom,level = ; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <688000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <644000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <510000000>; qcom,level = ; qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <362000000>; qcom,level = ; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <264000000>; qcom,level = ; qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; }; From 622f36bf2a9e8864a7580372297d30aba6f58f4f Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Fri, 31 Jan 2025 06:01:57 -0800 Subject: [PATCH 101/113] Revert "ARM: dts: msm: add chipid for KERA gpu" This reverts commit d69fe4603a743426896104ebf07f16f4b6c737b5. Change-Id: I62cd9540a085f737395592a783a51a30d9d4b510 --- gpu/kera-gpu.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 60ac5105..2cec634e 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -25,8 +25,6 @@ qcom,gpu-model = "Adreno716"; - qcom,chipid = <0x43020100>; - qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; From abb7b6ebbd8314772d4daed2c7cebeb376692cd6 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Thu, 9 Jan 2025 13:30:44 +0530 Subject: [PATCH 102/113] ARM: dts: msm: Add the nvmem cells for gaming fuse on kera gpu Define the nvmem cells for gaming fuse support on kera gpu. Change-Id: I3e316771845e01f1bba42040084be1f735099298 Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 136b0e82..ce19dd4c 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -66,6 +66,9 @@ , /* TURBO index=9 */ ; /* TURBO_L1 index=10 */ + nvmem-cells = <&gpu_gaming_bin>; + nvmem-cell-names = "gaming_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; From 8aac1b0fcd1b27b181bde4b39b5e2632e6fea49e Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 4 Dec 2024 17:57:10 +0530 Subject: [PATCH 103/113] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. Change-Id: I5c904b148f149f094dea735ba0a975862538dad6 Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu-pwrlevels.dtsi | 163 ++++++++++++++++++++++++++++-------- 1 file changed, 127 insertions(+), 36 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 5d8edc86..9839dafb 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -3,6 +3,18 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L2 0xa02f5ffd +#define ACD_LEVEL_TURBO_L1 0xa8285ffd +#define ACD_LEVEL_TURBO 0x88295ffd +#define ACD_LEVEL_NOM_L1 0xa8295ffd +#define ACD_LEVEL_NOM 0x882a5ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0xa82a5ffd +#define ACD_LEVEL_SVS 0xa82c5ffd +#define ACD_LEVEL_LOW_SVS 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd + &msm_gpu { /* Power levels */ qcom,gpu-pwrlevel-bins { @@ -19,106 +31,137 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <8>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <873000000>; qcom,level = ; qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <763000000>; qcom,level = ; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <688000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <644000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <510000000>; qcom,level = ; qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <362000000>; qcom,level = ; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <264000000>; qcom,level = ; qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -138,6 +181,8 @@ qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ @@ -149,6 +194,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ @@ -160,6 +207,7 @@ qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + qcom,acd-level = ; }; /* Nom */ @@ -171,6 +219,8 @@ qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -182,6 +232,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -193,6 +245,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -204,6 +258,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -215,6 +271,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -226,6 +284,8 @@ qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -233,106 +293,137 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <8>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0xf2>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <873000000>; qcom,level = ; qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <763000000>; qcom,level = ; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <688000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <644000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <510000000>; qcom,level = ; qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <362000000>; qcom,level = ; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <264000000>; qcom,level = ; qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; }; From 50079aa858bd7a3edf4a0c28090f66c3be8193fa Mon Sep 17 00:00:00 2001 From: Gayathri Veeragandam Date: Fri, 7 Feb 2025 10:30:27 +0530 Subject: [PATCH 104/113] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. Change-Id: Ibdd4774022e90ebc0c670ce2cadc071b988698d4 --- gpu/tuna-gpu-pwrlevels.dtsi | 143 +++++++++++++++++++++--------------- 1 file changed, 85 insertions(+), 58 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 9839dafb..aff3f7fa 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -4,16 +4,17 @@ */ /* ACD Control register values */ -#define ACD_LEVEL_TURBO_L2 0xa02f5ffd -#define ACD_LEVEL_TURBO_L1 0xa8285ffd -#define ACD_LEVEL_TURBO 0x88295ffd -#define ACD_LEVEL_NOM_L1 0xa8295ffd -#define ACD_LEVEL_NOM 0x882a5ffd -#define ACD_LEVEL_SVS_L2 0x882a5ffd -#define ACD_LEVEL_SVS_L1 0xa82a5ffd -#define ACD_LEVEL_SVS 0xa82c5ffd -#define ACD_LEVEL_LOW_SVS 0xc02c5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd +#define ACD_LEVEL_TURBO_L3 0xa8285ffd +#define ACD_LEVEL_TURBO_L2 0x88295ffd +#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_TURBO 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0xa82a5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS 0xc8295ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc8295ffd &msm_gpu { /* Power levels */ @@ -31,13 +32,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0>; - /* Turbo_L2 */ + /* Turbo_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L2 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -48,8 +62,8 @@ }; /* Turbo_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -61,34 +75,34 @@ }; /* Turbo */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <763000000>; qcom,level = ; @@ -100,8 +114,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <688000000>; qcom,level = ; @@ -113,8 +127,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <644000000>; qcom,level = ; @@ -126,12 +140,12 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -139,8 +153,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <362000000>; qcom,level = ; @@ -152,8 +166,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <264000000>; qcom,level = ; @@ -293,13 +307,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0xf2>; - /* Turbo_L2 */ + /* Turbo_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L2 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -310,8 +337,8 @@ }; /* Turbo_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -323,34 +350,34 @@ }; /* Turbo */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <763000000>; qcom,level = ; @@ -362,8 +389,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <688000000>; qcom,level = ; @@ -375,8 +402,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <644000000>; qcom,level = ; @@ -388,12 +415,12 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -401,8 +428,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <362000000>; qcom,level = ; @@ -414,8 +441,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <264000000>; qcom,level = ; From 6b69abc54c801cbe22fff9db1a787c771b9c3447 Mon Sep 17 00:00:00 2001 From: Gayathri Veeragandam Date: Fri, 7 Feb 2025 10:30:27 +0530 Subject: [PATCH 105/113] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. Change-Id: Ibdd4774022e90ebc0c670ce2cadc071b988698d4 Signed-off-by: Gayathri Veeragandam --- gpu/tuna-gpu-pwrlevels.dtsi | 141 +++++++++++++++++++++--------------- 1 file changed, 84 insertions(+), 57 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 9839dafb..73ee75e0 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -1,19 +1,20 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ /* ACD Control register values */ -#define ACD_LEVEL_TURBO_L2 0xa02f5ffd -#define ACD_LEVEL_TURBO_L1 0xa8285ffd -#define ACD_LEVEL_TURBO 0x88295ffd -#define ACD_LEVEL_NOM_L1 0xa8295ffd -#define ACD_LEVEL_NOM 0x882a5ffd -#define ACD_LEVEL_SVS_L2 0x882a5ffd -#define ACD_LEVEL_SVS_L1 0xa82a5ffd -#define ACD_LEVEL_SVS 0xa82c5ffd -#define ACD_LEVEL_LOW_SVS 0xc02c5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd +#define ACD_LEVEL_TURBO_L2 0xa8285ffd +#define ACD_LEVEL_TURBO_L1 0x88295ffd +#define ACD_LEVEL_TURBO_L0 0x882a5ffd +#define ACD_LEVEL_TURBO 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0xa82a5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS 0xc8295ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc8295ffd &msm_gpu { /* Power levels */ @@ -31,7 +32,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0>; /* Turbo_L2 */ @@ -50,7 +51,7 @@ /* Turbo_L1 */ qcom,gpu-pwrlevel@1 { reg = <1>; - qcom,gpu-freq = <1050000000>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -60,35 +61,48 @@ qcom,acd-level = ; }; - /* Turbo */ + /* Turbo_L0 */ qcom,gpu-pwrlevel@2 { reg = <2>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <763000000>; qcom,level = ; @@ -100,8 +114,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <688000000>; qcom,level = ; @@ -113,8 +127,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <644000000>; qcom,level = ; @@ -126,12 +140,12 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -139,8 +153,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <362000000>; qcom,level = ; @@ -152,8 +166,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <264000000>; qcom,level = ; @@ -193,7 +207,7 @@ qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; @@ -204,9 +218,9 @@ qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; @@ -255,7 +269,7 @@ qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -293,7 +307,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0xf2>; /* Turbo_L2 */ @@ -312,7 +326,7 @@ /* Turbo_L1 */ qcom,gpu-pwrlevel@1 { reg = <1>; - qcom,gpu-freq = <1050000000>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -322,35 +336,48 @@ qcom,acd-level = ; }; - /* Turbo */ + /* Turbo_L0 */ qcom,gpu-pwrlevel@2 { reg = <2>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <763000000>; qcom,level = ; @@ -362,8 +389,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <688000000>; qcom,level = ; @@ -375,8 +402,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <644000000>; qcom,level = ; @@ -388,12 +415,12 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -401,8 +428,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <362000000>; qcom,level = ; @@ -414,8 +441,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <264000000>; qcom,level = ; From 7633c0c31d0dd26888f36330a4bf3d86a4eb18c4 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Mon, 6 Jan 2025 12:20:35 +0530 Subject: [PATCH 106/113] ARM: dts: msm: Add support for 1150MHz frequency in Kera GPU Add support for 1150MHz frequency (Turbo L2) in Kera GPU. Change-Id: Ibe95ea6dbfaae4090879d59e45d746ce94eff096 Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu-pwrlevels.dtsi | 53 ++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi index bba8f52f..a84af42e 100644 --- a/gpu/kera-gpu-pwrlevels.dtsi +++ b/gpu/kera-gpu-pwrlevels.dtsi @@ -1,10 +1,10 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &msm_gpu { - qcom,initial-pwrlevel = <7>; + qcom,initial-pwrlevel = <8>; /* Power levels */ qcom,gpu-pwrlevels { @@ -13,9 +13,24 @@ #address-cells = <1>; #size-cells = <0>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1075000000>; qcom,level = ; @@ -29,8 +44,8 @@ }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <975000000>; qcom,level = ; @@ -44,8 +59,8 @@ }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -59,8 +74,8 @@ }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <796000000>; qcom,level = ; @@ -74,8 +89,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <724000000>; qcom,level = ; @@ -89,8 +104,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <645000000>; qcom,level = ; @@ -104,8 +119,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <515000000>; qcom,level = ; @@ -119,8 +134,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <345000000>; qcom,level = ; @@ -134,8 +149,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <259000000>; qcom,level = ; From 73f59b59a144b4187ec80f2621954d08418a8649 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Mon, 6 Jan 2025 12:20:35 +0530 Subject: [PATCH 107/113] ARM: dts: msm: Add support for 1150MHz frequency in Kera GPU Add support for 1150MHz frequency (Turbo L2) in Kera GPU. Change-Id: Ibe95ea6dbfaae4090879d59e45d746ce94eff096 Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu-pwrlevels.dtsi | 53 ++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi index bba8f52f..a84af42e 100644 --- a/gpu/kera-gpu-pwrlevels.dtsi +++ b/gpu/kera-gpu-pwrlevels.dtsi @@ -1,10 +1,10 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &msm_gpu { - qcom,initial-pwrlevel = <7>; + qcom,initial-pwrlevel = <8>; /* Power levels */ qcom,gpu-pwrlevels { @@ -13,9 +13,24 @@ #address-cells = <1>; #size-cells = <0>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1075000000>; qcom,level = ; @@ -29,8 +44,8 @@ }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <975000000>; qcom,level = ; @@ -44,8 +59,8 @@ }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -59,8 +74,8 @@ }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <796000000>; qcom,level = ; @@ -74,8 +89,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <724000000>; qcom,level = ; @@ -89,8 +104,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <645000000>; qcom,level = ; @@ -104,8 +119,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <515000000>; qcom,level = ; @@ -119,8 +134,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <345000000>; qcom,level = ; @@ -134,8 +149,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <259000000>; qcom,level = ; From 44360e21a924e93d9ff7380e898e1b993143ff14 Mon Sep 17 00:00:00 2001 From: Gayathri Veeragandam Date: Fri, 7 Feb 2025 10:30:27 +0530 Subject: [PATCH 108/113] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. Change-Id: Ic44a74c73793f8874076e62ae231b7e6326e897d Signed-off-by: Rohit Jadhav --- gpu/tuna-gpu-pwrlevels.dtsi | 141 +++++++++++++++++++++--------------- 1 file changed, 84 insertions(+), 57 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index b5cea40e..aff3f7fa 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -4,16 +4,17 @@ */ /* ACD Control register values */ -#define ACD_LEVEL_TURBO_L2 0xa02f5ffd -#define ACD_LEVEL_TURBO_L1 0xa8285ffd -#define ACD_LEVEL_TURBO 0x88295ffd -#define ACD_LEVEL_NOM_L1 0xa8295ffd -#define ACD_LEVEL_NOM 0x882a5ffd -#define ACD_LEVEL_SVS_L2 0x882a5ffd -#define ACD_LEVEL_SVS_L1 0xa82a5ffd -#define ACD_LEVEL_SVS 0xa82c5ffd -#define ACD_LEVEL_LOW_SVS 0xc02c5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd +#define ACD_LEVEL_TURBO_L3 0xa8285ffd +#define ACD_LEVEL_TURBO_L2 0x88295ffd +#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_TURBO 0x882a5ffd +#define ACD_LEVEL_NOM_L1 0xa82a5ffd +#define ACD_LEVEL_NOM 0x882b5ffd +#define ACD_LEVEL_SVS_L2 0x882b5ffd +#define ACD_LEVEL_SVS_L1 0xa82b5ffd +#define ACD_LEVEL_SVS 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS 0xc8295ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc8295ffd &msm_gpu { /* Power levels */ @@ -31,13 +32,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0>; - /* Turbo_L2 */ + /* Turbo_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L2 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -48,8 +62,8 @@ }; /* Turbo_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -61,34 +75,34 @@ }; /* Turbo */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <763000000>; qcom,level = ; @@ -100,8 +114,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <688000000>; qcom,level = ; @@ -113,8 +127,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <644000000>; qcom,level = ; @@ -126,8 +140,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <510000000>; qcom,level = ; @@ -139,8 +153,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <362000000>; qcom,level = ; @@ -152,8 +166,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <264000000>; qcom,level = ; @@ -293,13 +307,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <9>; + qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0xf2>; - /* Turbo_L2 */ + /* Turbo_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L2 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -310,8 +337,8 @@ }; /* Turbo_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -323,34 +350,34 @@ }; /* Turbo */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <763000000>; qcom,level = ; @@ -362,8 +389,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <688000000>; qcom,level = ; @@ -375,8 +402,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <644000000>; qcom,level = ; @@ -388,12 +415,12 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -401,8 +428,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <362000000>; qcom,level = ; @@ -414,8 +441,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <264000000>; qcom,level = ; From fd59987095e8fd8159f838b478f2023101634c37 Mon Sep 17 00:00:00 2001 From: Sanjay Yadav Date: Wed, 19 Feb 2025 22:27:25 +0530 Subject: [PATCH 109/113] ARM: dts: msm: Add Kera GPU ACD values Add ACD control register values and support for Kera GPU. Change-Id: Idfb20fe8b46655fadf121d2a8192a4fbc42c051c Signed-off-by: Sanjay Yadav --- gpu/kera-gpu-pwrlevels.dtsi | 20 ++++++++++++++++++++ gpu/kera-gpu.dtsi | 15 +++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi index a84af42e..3f522a55 100644 --- a/gpu/kera-gpu-pwrlevels.dtsi +++ b/gpu/kera-gpu-pwrlevels.dtsi @@ -26,6 +26,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = ; }; /* Turbo_L1 */ @@ -41,6 +43,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = ; }; /* Turbo */ @@ -56,6 +60,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = ; }; /* Nom_L1 */ @@ -71,6 +77,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = ; }; /* Nom */ @@ -86,6 +94,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -101,6 +111,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -116,6 +128,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -131,6 +145,8 @@ qcom,bus-freq-ddr8 = <4>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <5>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -146,6 +162,8 @@ qcom,bus-freq-ddr8 = <2>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <4>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -161,6 +179,8 @@ qcom,bus-freq-ddr8 = <2>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <4>; + + qcom,acd-level = ; }; }; }; diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 24fea604..315e1028 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -5,6 +5,18 @@ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) +/* ACD Control register values */ +#define ACD_LEVEL_Turbo_L2 0xa8295ffd +#define ACD_LEVEL_Turbo_L1 0xa82a5ffd +#define ACD_LEVEL_Turbo 0x882c5ffd +#define ACD_LEVEL_Nominal_L1 0x882d5ffd +#define ACD_LEVEL_Nominal 0x882d5ffd +#define ACD_LEVEL_SVS_L2 0xa82d5ffd +#define ACD_LEVEL_SVS_L1 0x882f5ffd +#define ACD_LEVEL_SVS 0Xc02d5ffd +#define ACD_LEVEL_LowSVS 0Xc82f5ffd +#define ACD_LEVEL_LowSVS_D1 0Xc82f5ffd + &msm_gpu { compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0"; status = "ok"; @@ -169,5 +181,8 @@ iommus = <&kgsl_smmu 0x5 0x000>; qcom,iommu-dma = "disabled"; + + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; }; }; From 4a42af5e4c02c88d7399fc85f2d7c599d5bc6ebf Mon Sep 17 00:00:00 2001 From: Sanjay Yadav Date: Wed, 19 Feb 2025 22:27:25 +0530 Subject: [PATCH 110/113] ARM: dts: msm: Add Kera GPU ACD values Add ACD control register values and support for Kera GPU. Change-Id: Idfb20fe8b46655fadf121d2a8192a4fbc42c051c Signed-off-by: Sanjay Yadav --- gpu/kera-gpu-pwrlevels.dtsi | 20 ++++++++++++++++++++ gpu/kera-gpu.dtsi | 15 +++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi index a84af42e..3f522a55 100644 --- a/gpu/kera-gpu-pwrlevels.dtsi +++ b/gpu/kera-gpu-pwrlevels.dtsi @@ -26,6 +26,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = ; }; /* Turbo_L1 */ @@ -41,6 +43,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = ; }; /* Turbo */ @@ -56,6 +60,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = ; }; /* Nom_L1 */ @@ -71,6 +77,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = ; }; /* Nom */ @@ -86,6 +94,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -101,6 +111,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -116,6 +128,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -131,6 +145,8 @@ qcom,bus-freq-ddr8 = <4>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <5>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -146,6 +162,8 @@ qcom,bus-freq-ddr8 = <2>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <4>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -161,6 +179,8 @@ qcom,bus-freq-ddr8 = <2>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <4>; + + qcom,acd-level = ; }; }; }; diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 24fea604..315e1028 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -5,6 +5,18 @@ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) +/* ACD Control register values */ +#define ACD_LEVEL_Turbo_L2 0xa8295ffd +#define ACD_LEVEL_Turbo_L1 0xa82a5ffd +#define ACD_LEVEL_Turbo 0x882c5ffd +#define ACD_LEVEL_Nominal_L1 0x882d5ffd +#define ACD_LEVEL_Nominal 0x882d5ffd +#define ACD_LEVEL_SVS_L2 0xa82d5ffd +#define ACD_LEVEL_SVS_L1 0x882f5ffd +#define ACD_LEVEL_SVS 0Xc02d5ffd +#define ACD_LEVEL_LowSVS 0Xc82f5ffd +#define ACD_LEVEL_LowSVS_D1 0Xc82f5ffd + &msm_gpu { compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0"; status = "ok"; @@ -169,5 +181,8 @@ iommus = <&kgsl_smmu 0x5 0x000>; qcom,iommu-dma = "disabled"; + + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; }; }; From ce5d522804fc2ed0f31fb080018a1833a1b14aee Mon Sep 17 00:00:00 2001 From: Sanjay Yadav Date: Thu, 13 Mar 2025 15:03:35 +0530 Subject: [PATCH 111/113] ARM: dts: msm: Remove GPU model reference from Kera GPU Remove GPU model reference from Kera GPU. Change-Id: I723b521c23386ed6f50cb32b87b3053cb712aed6 Signed-off-by: Sanjay Yadav --- gpu/kera-gpu.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 24fea604..eb241e89 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -26,8 +26,6 @@ clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb", "gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk"; - qcom,gpu-model = "Adreno716"; - qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; From d259f15917ecffc5dc3fe198ab369d51904c3de6 Mon Sep 17 00:00:00 2001 From: Sanjay Yadav Date: Thu, 13 Mar 2025 15:03:35 +0530 Subject: [PATCH 112/113] ARM: dts: msm: Remove GPU model reference from Kera GPU Remove GPU model reference from Kera GPU. Change-Id: I723b521c23386ed6f50cb32b87b3053cb712aed6 Signed-off-by: Sanjay Yadav --- gpu/kera-gpu.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 315e1028..0bf1cd1a 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -38,8 +38,6 @@ clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb", "gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk"; - qcom,gpu-model = "Adreno716"; - qcom,min-access-length = <32>; qcom,ubwc-mode = <4>; From 295adba43b4a2f9656c9ca7bc8614e1663839852 Mon Sep 17 00:00:00 2001 From: Gayathri Veeragandam Date: Fri, 7 Feb 2025 10:30:27 +0530 Subject: [PATCH 113/113] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. updating PS#5 of Ibdd4774022e90ebc0c670ce2cadc071b988698d4 Change-Id: I4aca1dfe66a24e80471ad22a5c1f373d7b2a4e16 Signed-off-by: Rohit Jadhav --- gpu/tuna-gpu-pwrlevels.dtsi | 84 ++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index aff3f7fa..73ee75e0 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ /* ACD Control register values */ -#define ACD_LEVEL_TURBO_L3 0xa8285ffd -#define ACD_LEVEL_TURBO_L2 0x88295ffd -#define ACD_LEVEL_TURBO_L1 0x882a5ffd +#define ACD_LEVEL_TURBO_L2 0xa8285ffd +#define ACD_LEVEL_TURBO_L1 0x88295ffd +#define ACD_LEVEL_TURBO_L0 0x882a5ffd #define ACD_LEVEL_TURBO 0x882a5ffd #define ACD_LEVEL_NOM_L1 0xa82a5ffd #define ACD_LEVEL_NOM 0x882b5ffd @@ -35,23 +35,10 @@ qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0>; - /* Turbo_L3 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* Turbo_L2 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -62,9 +49,9 @@ }; /* Turbo_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <1050000000>; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -74,6 +61,19 @@ qcom,acd-level = ; }; + /* Turbo_L0 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + /* Turbo */ qcom,gpu-pwrlevel@3 { reg = <3>; @@ -207,7 +207,7 @@ qcom,bus-freq = <10>; qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,bus-max = <11>; qcom,acd-level = ; }; @@ -218,9 +218,9 @@ qcom,gpu-freq = <873000000>; qcom,level = ; - qcom,bus-freq = <9>; + qcom,bus-freq = <10>; qcom,bus-min = <7>; - qcom,bus-max = <9>; + qcom,bus-max = <11>; qcom,acd-level = ; }; @@ -269,7 +269,7 @@ qcom,gpu-freq = <510000000>; qcom,level = ; - qcom,bus-freq = <4>; + qcom,bus-freq = <6>; qcom,bus-min = <2>; qcom,bus-max = <6>; @@ -310,23 +310,10 @@ qcom,initial-pwrlevel = <10>; qcom,speed-bin = <0xf2>; - /* Turbo_L3 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* Turbo_L2 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -337,9 +324,9 @@ }; /* Turbo_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <1050000000>; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -349,6 +336,19 @@ qcom,acd-level = ; }; + /* Turbo_L0 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + /* Turbo */ qcom,gpu-pwrlevel@3 { reg = <3>;