Merge "ARM: dts: msm: Add M31 HS and QMP SS USB PHY configuration on sun"
This commit is contained in:
qctecmdr
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Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
e0b8859b2c
@@ -3188,4 +3188,33 @@
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};
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};
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};
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usb_phy_ps: usb_phy_ps {
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usb3phy_portselect_default: usb3phy_portselect_default {
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mux {
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pins = "gpio61";
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function = "usb_phy";
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};
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config {
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pins = "gpio61";
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bias-pull-down;
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drive-strength = <2>;
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};
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};
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usb3phy_portselect_gpio: usb3phy_portselect_gpio {
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mux {
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pins = "gpio61";
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function = "gpio";
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};
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config {
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pins = "gpio61";
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drive-strength = <2>;
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bias-pull-down;
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input-enable;
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};
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};
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};
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};
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@@ -3,6 +3,9 @@
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/phy/qcom,usb3-3nm-qmp-combo.h>
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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@@ -43,6 +46,7 @@
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dma-coherent;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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@@ -57,4 +61,241 @@
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usb-role-switch;
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};
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};
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/* USB port related High Speed PHY */
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eusb2_phy0: hsphy@88e3000 {
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compatible = "qcom,usb-m31-eusb2-phy";
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reg = <0x88e3000 0x29C>,
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<0x088e2000 0x4>,
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<0x0c278000 0x4>;
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reg-names = "eusb2_phy_base",
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"eud_enable_reg",
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"eud_detect_reg";
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vdd-supply = <&pm_v8d_l2>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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vdda12-supply = <&pm_v8g_l3>;
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clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
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<&tcsrcc TCSR_USB2_CLKREF_EN>;
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clock-names = "ref_clk_src", "ref_clk";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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/* USB port related QMP USB DP Combo PHY */
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usb_qmp_dp_phy: ssphy@88e8000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88e8000 0x3000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&pm_v8d_l2>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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qcom,vdd-max-load-uA = <47000>;
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core-supply = <&pm_v8g_l3>;
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usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
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<&rpmhcc RPMH_CXO_PAD_CLK>,
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<&tcsrcc TCSR_USB3_CLKREF_EN>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
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"pipe_clk_ext_src", "ref_clk_src",
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"ref_clk", "com_aux_clk";
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resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "global_phy_reset", "phy_reset";
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pinctrl-names = "default";
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pinctrl-0 = <&usb3phy_portselect_default>;
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qcom,qmp-phy-reg-offset =
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<USB3_DP_PCS_PCS_STATUS1
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USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
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USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
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USB3_DP_PCS_POWER_DOWN_CONTROL
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USB3_DP_PCS_SW_RESET
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USB3_DP_PCS_START_CONTROL
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0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
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USB3_DP_COM_POWER_DOWN_CTRL
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USB3_DP_COM_SW_RESET
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USB3_DP_COM_RESET_OVRD_CTRL
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USB3_DP_COM_PHY_MODE_CTRL
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USB3_DP_COM_TYPEC_CTRL
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USB3_DP_PCS_AON_CLAMP_ENABLE>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value> based on tsmcn3e_USB3_Gen2_Seq v1.6 */
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<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
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USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
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USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
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USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04
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USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41
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USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41
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USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75
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USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01
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USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01
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USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25
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USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01
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USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
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USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
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USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A
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USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41
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USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75
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USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01
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USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25
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USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02
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USB3_DP_QSERDES_COM_BG_TIMER 0x0A
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USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
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USB3_DP_QSERDES_COM_SSC_PER1 0x62
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USB3_DP_QSERDES_COM_SSC_PER2 0x02
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USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C
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USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
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USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14
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USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04
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USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20
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USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16
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USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
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USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4A
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USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x36
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USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09
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USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5
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USB3_DP_QSERDES_TXA_LANE_MODE_3 0x11
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USB3_DP_QSERDES_TXA_LANE_MODE_4 0x31
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USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F
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USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
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USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
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USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
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USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
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USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
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USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
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USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
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USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
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USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
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USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A
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USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x20
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
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USB3_DP_QSERDES_RXA_GM_CAL 0x13
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0E
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
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USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x27
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USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x0C
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USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
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USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
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USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x22
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x12
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xDA
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3F
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
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USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x19
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x09
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x91
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0xB7
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xAA
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USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
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USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
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USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
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USB3_DP_QSERDES_RXA_VTH_CODE 0x10
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USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14
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USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09
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USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5
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USB3_DP_QSERDES_TXB_LANE_MODE_3 0x11
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USB3_DP_QSERDES_TXB_LANE_MODE_4 0x31
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USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F
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USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
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USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05
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USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
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USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
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USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
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USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
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USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
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USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
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USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
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USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A
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USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x20
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
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USB3_DP_QSERDES_RXB_GM_CAL 0x13
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0E
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
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USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x27
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USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x0C
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USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
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USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
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USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x22
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x12
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xDA
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3F
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
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USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x19
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x09
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x91
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0xB7
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xAA
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USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
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USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
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USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
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USB3_DP_QSERDES_RXB_VTH_CODE 0x10
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USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14
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USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08
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USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
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USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
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USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
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USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
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USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
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USB3_DP_PCS_RX_SIGDET_LVL 0x99
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USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
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USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
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USB3_DP_PCS_CDR_RESET_TIME 0x0A
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USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
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USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
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USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
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USB3_DP_PCS_EQ_CONFIG1 0x4B
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USB3_DP_PCS_EQ_CONFIG5 0x10
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USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
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USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
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USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
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USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
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USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
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};
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};
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