From 1fb24b5e920ba3d21df4b13f70e2eeaa7b46bdaa Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Wed, 1 Nov 2023 16:09:58 -0700 Subject: [PATCH] ARM: dts: msm: Add M31 HS and QMP SS USB PHY configuration on sun Add M31 eUSB2 and QMP SS PHY nodes to sun. Add required dependencies in pinctrl as well for HW based SS lane detection. Change-Id: Ib1546aa7d92853a88a05d0bbc836ec4caac40960 Signed-off-by: Ronak Vijay Raheja --- qcom/sun-pinctrl.dtsi | 29 +++++ qcom/sun-usb.dtsi | 241 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 270 insertions(+) diff --git a/qcom/sun-pinctrl.dtsi b/qcom/sun-pinctrl.dtsi index 6bfde5c7..30c19f83 100644 --- a/qcom/sun-pinctrl.dtsi +++ b/qcom/sun-pinctrl.dtsi @@ -3106,4 +3106,33 @@ }; }; }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio61"; + function = "usb_phy"; + }; + + config { + pins = "gpio61"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + usb3phy_portselect_gpio: usb3phy_portselect_gpio { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; }; diff --git a/qcom/sun-usb.dtsi b/qcom/sun-usb.dtsi index b68f8135..da1bed60 100644 --- a/qcom/sun-usb.dtsi +++ b/qcom/sun-usb.dtsi @@ -3,6 +3,9 @@ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; @@ -43,6 +46,7 @@ dma-coherent; interrupts = ; + usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; @@ -57,4 +61,241 @@ usb-role-switch; }; }; + + /* USB port related High Speed PHY */ + eusb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-m31-eusb2-phy"; + reg = <0x88e3000 0x29C>, + <0x088e2000 0x4>, + <0x0c278000 0x4>; + reg-names = "eusb2_phy_base", + "eud_enable_reg", + "eud_detect_reg"; + + vdd-supply = <&pm_v8d_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + vdda12-supply = <&pm_v8g_l3>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm_v8d_l2>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm_v8g_l3>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* based on tsmcn3e_USB3_Gen2_Seq v1.6 */ + ; + }; };