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Merge "ARM: dts: msm: Add support for CAMCC, CAMBISTMCLKCC and DISPCC on Kera"

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QCTECMDR Service
2024-10-25 02:40:26 -07:00
committed by Gerrit - the friendly Code Review server
parent 6468a3c87a 5de6529a5c
commit e08a177f44
2 changed files with 48 additions and 15 deletions
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61
qcom/kera.dtsi
View File

@@ -1180,22 +1180,58 @@
}; };
cambistmclkcc: clock-controller@1760000 { cambistmclkcc: clock-controller@1760000 {
compatible = "qcom,dummycc"; compatible = "qcom,tuna-cambistmclkcc", "syscon";
clock-output-names = "cambistmclkcc_clocks"; reg = <0x1760000 0x6000>;
reg-name = "cc_base";
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&gcc GCC_CAM_BIST_MCLK_AHB_CLK>;
clock-names = "bi_tcxo",
"sleep_clk",
"iface";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
camcc: clock-controller@ade0000 { camcc: clock-controller@ade0000 {
compatible = "qcom,dummycc"; compatible = "qcom,kera-camcc", "syscon";
clock-output-names = "camcc_clocks"; reg = <0xade0000 0x20000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk",
"iface";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
dispcc_crm: syscon@af27800 {
compatible = "syscon";
reg = <0xaf27800 0x2000>;
};
dispcc: clock-controller@af00000 { dispcc: clock-controller@af00000 {
compatible = "qcom,dummycc"; compatible = "qcom,tuna-dispcc", "syscon";
clock-output-names = "dispcc_clocks"; reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk",
"iface";
qcom,disp_crm-crmc = <&dispcc_crm>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -1735,42 +1771,39 @@
#include "ipcc-test-no-slpi.dtsi" #include "ipcc-test-no-slpi.dtsi"
&cam_cc_ipe_0_gdsc { &cam_cc_ipe_0_gdsc {
compatible = "regulator-fixed";
status = "ok"; status = "ok";
}; };
&cam_cc_ofe_gdsc { &cam_cc_ofe_gdsc {
compatible = "regulator-fixed";
status = "ok"; status = "ok";
}; };
&cam_cc_tfe_0_gdsc { &cam_cc_tfe_0_gdsc {
compatible = "regulator-fixed";
status = "ok"; status = "ok";
}; };
&cam_cc_tfe_1_gdsc { &cam_cc_tfe_1_gdsc {
compatible = "regulator-fixed";
status = "ok"; status = "ok";
}; };
&cam_cc_tfe_2_gdsc { &cam_cc_tfe_2_gdsc {
compatible = "regulator-fixed";
status = "ok"; status = "ok";
}; };
&cam_cc_titan_top_gdsc { &cam_cc_titan_top_gdsc {
compatible = "regulator-fixed"; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
interconnect-names = "mmnoc";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&disp_cc_mdss_core_gdsc { &disp_cc_mdss_core_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&disp_cc_mdss_core_int2_gdsc { &disp_cc_mdss_core_int2_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };

2
qcom/tuna.dtsi
View File

@@ -1713,7 +1713,7 @@
"bi_tcxo_ao", "bi_tcxo_ao",
"sleep_clk", "sleep_clk",
"iface"; "iface";
qcom,dispcc_crm-crmc = <&dispcc_crm>; qcom,disp_crm-crmc = <&dispcc_crm>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;