From 5de6529a5cf982563b5e820b17deecb04fd2b160 Mon Sep 17 00:00:00 2001
From: Ajit Pandey <quic_ajipan@quicinc.com>
Date: Tue, 17 Sep 2024 15:51:16 +0530
Subject: [PATCH] ARM: dts: msm: Add support for CAMCC, CAMBISTMCLKCC and
 DISPCC on Kera

Add support for camera, cambistmclk and display clock controller nodes
on Kera platform. While at it, move camcc and dispcc gdsc's to real
alongwith required interconnect voting for camcc_titan_top gdsc and
updated dispcc crm property name for tuna platform.

Change-Id: I844a35d688eb4050212e11e81eae1aaa55a4a24f
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
---
 qcom/kera.dtsi | 61 ++++++++++++++++++++++++++++++++++++++------------
 qcom/tuna.dtsi |  2 +-
 2 files changed, 48 insertions(+), 15 deletions(-)

diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index d349e893..0859d024 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -1163,22 +1163,58 @@
 	};
 
 	cambistmclkcc: clock-controller@1760000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "cambistmclkcc_clocks";
+		compatible = "qcom,tuna-cambistmclkcc", "syscon";
+		reg = <0x1760000 0x6000>;
+		reg-name = "cc_base";
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&sleep_clk>,
+			 <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>;
+		clock-names = "bi_tcxo",
+			      "sleep_clk",
+			      "iface";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
 	camcc: clock-controller@ade0000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "camcc_clocks";
+		compatible = "qcom,kera-camcc", "syscon";
+		reg = <0xade0000 0x20000>;
+		reg-name = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK_A>,
+			 <&sleep_clk>,
+			 <&gcc GCC_CAMERA_AHB_CLK>;
+		clock-names = "bi_tcxo",
+			      "bi_tcxo_ao",
+			      "sleep_clk",
+			      "iface";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
+	dispcc_crm: syscon@af27800 {
+		compatible = "syscon";
+		reg = <0xaf27800 0x2000>;
+	};
+
 	dispcc: clock-controller@af00000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "dispcc_clocks";
+		compatible = "qcom,tuna-dispcc", "syscon";
+		reg = <0xaf00000 0x20000>;
+		reg-name = "cc_base";
+		vdd_mm-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK_A>,
+			 <&sleep_clk>,
+			 <&gcc GCC_DISP_AHB_CLK>;
+		clock-names = "bi_tcxo",
+			      "bi_tcxo_ao",
+			      "sleep_clk",
+			      "iface";
+		qcom,disp_crm-crmc = <&dispcc_crm>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -1718,42 +1754,39 @@
 #include "ipcc-test-no-slpi.dtsi"
 
 &cam_cc_ipe_0_gdsc {
-	compatible = "regulator-fixed";
 	status = "ok";
 };
 
 &cam_cc_ofe_gdsc {
-	compatible = "regulator-fixed";
 	status = "ok";
 };
 
 &cam_cc_tfe_0_gdsc {
-	compatible = "regulator-fixed";
 	status = "ok";
 };
 
 &cam_cc_tfe_1_gdsc {
-	compatible = "regulator-fixed";
 	status = "ok";
 };
 
 &cam_cc_tfe_2_gdsc {
-	compatible = "regulator-fixed";
 	status = "ok";
 };
 
 &cam_cc_titan_top_gdsc {
-	compatible = "regulator-fixed";
+	interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+	interconnect-names = "mmnoc";
+	parent-supply = <&VDD_CX_LEVEL>;
 	status = "ok";
 };
 
 &disp_cc_mdss_core_gdsc {
-	compatible = "regulator-fixed";
+	parent-supply = <&VDD_CX_LEVEL>;
 	status = "ok";
 };
 
 &disp_cc_mdss_core_int2_gdsc {
-	compatible = "regulator-fixed";
+	parent-supply = <&VDD_CX_LEVEL>;
 	status = "ok";
 };
 
diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index d51d206e..979a84e1 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -1708,7 +1708,7 @@
 			      "bi_tcxo_ao",
 			      "sleep_clk",
 			      "iface";
-		qcom,dispcc_crm-crmc = <&dispcc_crm>;
+		qcom,disp_crm-crmc = <&dispcc_crm>;
 		#power-domain-cells = <1>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;