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ARM: dts: qcom: update clk div factor entry for TX and VA macros

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Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.

Change-Id: I29d5d4fb0fbbae4b2bd3c121f1b6f7a6d34e9cd2
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
This commit is contained in:
Vangala, Amarnath
2024-09-02 23:19:10 +05:30
parent 6e408f41e3
commit da99ab8300
1 changed files with 26 additions and 2 deletions
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28
sun-audio-overlay.dtsi
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@@ -35,7 +35,19 @@
reg = <0x7660000 0x0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,va-dmic-sample-rate = <600000>;
/*
* Clk divding factors for each DMIC pair.
* Valid entries for each DMIC pair:
* 2, 3, 4, 6, 8, 16
*
* These factors are translated to corresponding config values
* for the following registers,
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
*/
qcom,va-dmic-clk-div-factor = <16 16 16 16>;
qcom,va-clk-mux-select = <1>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,use-clk-id = <VA_CORE_CLK>;
@@ -81,7 +93,19 @@
compatible = "qcom,lpass-cdc-tx-macro";
reg = <0x6AE0000 0x0>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,tx-dmic-sample-rate = <2400000>;
/*
* Clk divding factors for each DMIC pair.
* Valid entries for each DMIC pair:
* 2, 3, 4, 6, 8, 16
*
* These factors are translated to corresponding config values
* for the following registers,
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
*/
qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
qcom,is-used-swr-gpio = <0>;
};