From da99ab8300b9169751817465c4700695d16d9110 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Mon, 2 Sep 2024 23:19:10 +0530 Subject: [PATCH] ARM: dts: qcom: update clk div factor entry for TX and VA macros Update clk div factor entries for TX and VA macros to reflect proper HW configuration. Change-Id: I29d5d4fb0fbbae4b2bd3c121f1b6f7a6d34e9cd2 Signed-off-by: Vangala, Amarnath --- sun-audio-overlay.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/sun-audio-overlay.dtsi b/sun-audio-overlay.dtsi index dc9c7340..ed513359 100644 --- a/sun-audio-overlay.dtsi +++ b/sun-audio-overlay.dtsi @@ -35,7 +35,19 @@ reg = <0x7660000 0x0>; clock-names = "lpass_audio_hw_vote"; clocks = <&lpass_audio_hw_vote 0>; - qcom,va-dmic-sample-rate = <600000>; + /* + * Clk divding factors for each DMIC pair. + * Valid entries for each DMIC pair: + * 2, 3, 4, 6, 8, 16 + * + * These factors are translated to corresponding config values + * for the following registers, + * -- LPASS_VA_TOP_CSR_DMIC0_CTL, + * -- LPASS_VA_TOP_CSR_DMIC1_CTL, + * -- LPASS_VA_TOP_CSR_DMIC2_CTL, + * -- LPASS_VA_TOP_CSR_DMIC3_CTL, + */ + qcom,va-dmic-clk-div-factor = <16 16 16 16>; qcom,va-clk-mux-select = <1>; qcom,default-clk-id = ; qcom,use-clk-id = ; @@ -81,7 +93,19 @@ compatible = "qcom,lpass-cdc-tx-macro"; reg = <0x6AE0000 0x0>; qcom,default-clk-id = ; - qcom,tx-dmic-sample-rate = <2400000>; + /* + * Clk divding factors for each DMIC pair. + * Valid entries for each DMIC pair: + * 2, 3, 4, 6, 8, 16 + * + * These factors are translated to corresponding config values + * for the following registers, + * -- LPASS_VA_TOP_CSR_DMIC0_CTL, + * -- LPASS_VA_TOP_CSR_DMIC1_CTL, + * -- LPASS_VA_TOP_CSR_DMIC2_CTL, + * -- LPASS_VA_TOP_CSR_DMIC3_CTL, + */ + qcom,tx-dmic-clk-div-factor = <4 4 4 4>; qcom,is-used-swr-gpio = <0>; };