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Merge "ARM: dts: qcom: Add cooling-cells for cpu in monaco"

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QCTECMDR Service
2024-10-17 06:59:31 -07:00
committed by Gerrit - the friendly Code Review server
parent 9b96e0ba0b 1402955d21
commit d9b2e0a9cd
1 changed files with 3 additions and 0 deletions
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3
qcom/monaco.dtsi
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@@ -84,6 +84,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>; qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_1: l1-icache { L1_I_1: l1-icache {
compatible = "cache"; compatible = "cache";
@@ -109,6 +110,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>; qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_2: l1-icache { L1_I_2: l1-icache {
compatible = "cache"; compatible = "cache";
@@ -134,6 +136,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>; qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_3: l1-icache { L1_I_3: l1-icache {
compatible = "cache"; compatible = "cache";