Merge 5468eee8ad on remote branch
Change-Id: Iae36aefbd8cb6ca86e7204050f3dfa9d67bc2435
This commit is contained in:
Linux Build Service Account
6
Kbuild
6
Kbuild
@@ -1,3 +1,4 @@
|
||||
ifneq ($(CONFIG_ARCH_QTI_VM), y)
|
||||
dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
|
||||
display/sun-sde-display-cdp-overlay.dtbo \
|
||||
display/sun-sde-display-mtp-overlay.dtbo \
|
||||
@@ -14,6 +15,11 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
|
||||
display/sun-sde-display-mtp-nfc-overlay.dtbo \
|
||||
display/sun-sde-display-cdp-v8-overlay.dtbo \
|
||||
display/sun-sde-display-mtp-v8-overlay.dtbo
|
||||
else
|
||||
dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
|
||||
display/trustedvm-sun-sde-display-mtp-overlay.dtbo \
|
||||
display/trustedvm-sun-sde-display-qrd-overlay.dtbo
|
||||
endif
|
||||
|
||||
always-y := $(dtb-y) $(dtbo-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
||||
@@ -404,6 +404,12 @@ Optional properties:
|
||||
hardware.
|
||||
- qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE
|
||||
wrapper hardware block instance.
|
||||
- qcom,sde-dspp-aiqe-aiscaler-off: Array of u32 values indicating the offset of each AIQE
|
||||
AI Scaler block relative to its parent DSPP block.
|
||||
- qcom,sde-dspp-aiqe-aiscaler-version: A u32 value indicating the version of the AIQE AI Scaler
|
||||
hardware.
|
||||
- qcom,sde-dspp-aiqe-aiscaler-size: A u32 value indicating the shared memory size of each AIQE
|
||||
AI Scaler hardware block instance.
|
||||
- qcom,sde-aiqe-has-feature-mdnie: Boolean property indicating the presence of AIQE feature mDNIe
|
||||
hardware.
|
||||
- qcom,sde-aiqe-has-feature-abc: Boolean property indicating the presence of AIQE feature ABC
|
||||
@@ -412,6 +418,10 @@ Optional properties:
|
||||
hardware.
|
||||
- qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR
|
||||
hardware.
|
||||
- qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature
|
||||
AI Scaler hardware.
|
||||
- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device.
|
||||
- nvmem-cell-names: nvmem cell name.
|
||||
- qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base.
|
||||
- qcom,sde-lm-noise-version: A u32 value indicating the noise layer version.
|
||||
- qcom,sde-vbif-id: Array of vbif ids corresponding to the
|
||||
@@ -561,9 +571,13 @@ Optional properties:
|
||||
silver or gold or gold+.
|
||||
- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
|
||||
- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
|
||||
- qcom,sde-soccp-controller: The phandle for the soccp controller.
|
||||
This value is optional and only required for targets with SOCCP.
|
||||
- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
|
||||
- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
|
||||
for ipcc registers access.
|
||||
- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg
|
||||
offset.
|
||||
- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
|
||||
rotation.
|
||||
- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
|
||||
@@ -903,8 +917,10 @@ Example:
|
||||
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||
|
||||
qcom,sde-soccp-controller = <&soccp_pas>;
|
||||
qcom,sde-ipcc-protocol-id = <0x2>;
|
||||
qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
|
||||
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
|
||||
|
||||
qcom,sde-vbif-off = <0 0>;
|
||||
qcom,sde-vbif-id = <0 1>;
|
||||
@@ -974,6 +990,9 @@ Example:
|
||||
qcom,sde-reg-dma-xin-id = <7>;
|
||||
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
|
||||
|
||||
nvmem-cells = <&ssip_config>;
|
||||
nvmem-cell-names = "ssip_config";
|
||||
|
||||
qcom,sde-sspp-vig-blocks {
|
||||
vcm@0 {
|
||||
cell-index = <0>;
|
||||
|
||||
@@ -12,10 +12,12 @@
|
||||
compatible = "qcom,sde-kms";
|
||||
reg = <0x0ae00000 0x93800>,
|
||||
<0x0aeb0000 0x2008>,
|
||||
<0x0af80000 0x7000>;
|
||||
<0x0af80000 0x7000>,
|
||||
<0x400000 0x2000>;
|
||||
reg-names = "mdp_phys",
|
||||
"vbif_phys",
|
||||
"regdma_phys";
|
||||
"regdma_phys",
|
||||
"ipcc_reg";
|
||||
|
||||
/* interrupt config */
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -205,10 +207,15 @@
|
||||
qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>;
|
||||
qcom,sde-dspp-aiqe-wrapper-size = <0x1c>;
|
||||
|
||||
qcom,sde-dspp-aiqe-aiscaler-off = <0x30000 0xffffffff>;
|
||||
qcom,sde-dspp-aiqe-aiscaler-version = <0x00010000>;
|
||||
qcom,sde-dspp-aiqe-aiscaler-size = <0x7d0>;
|
||||
|
||||
qcom,sde-aiqe-has-feature-mdnie;
|
||||
qcom,sde-aiqe-has-feature-abc;
|
||||
qcom,sde-aiqe-has-feature-ssrc;
|
||||
qcom,sde-aiqe-has-feature-copr;
|
||||
qcom,sde-aiqe-has-feature-aiscaler;
|
||||
|
||||
qcom,sde-lm-noise-off = <0x320>;
|
||||
qcom,sde-lm-noise-version = <0x00010000>;
|
||||
@@ -256,6 +263,11 @@
|
||||
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||
|
||||
qcom,sde-ipcc-protocol-id = <0x4>;
|
||||
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
|
||||
qcom,sde-soccp-controller = <&soccp_pas>;
|
||||
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
qcom,sde-reg-dma-off = <0 0x800>;
|
||||
qcom,sde-reg-dma-id = <0 1>;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi"
|
||||
@@ -349,6 +349,12 @@
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
@@ -369,6 +375,12 @@
|
||||
|
||||
&dsi_nt37801_amoled_video_cphy {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
@@ -382,6 +394,12 @@
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
@@ -396,6 +414,12 @@
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
|
||||
@@ -1,10 +1,46 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
@@ -25,6 +61,16 @@
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
@@ -35,6 +81,44 @@
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
|
||||
@@ -1,10 +1,46 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
@@ -45,6 +81,104 @@
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
|
||||
};
|
||||
@@ -57,3 +191,10 @@
|
||||
&dsi_nt37801_amoled_video>;
|
||||
};
|
||||
};
|
||||
|
||||
&battery_charger {
|
||||
qcom,display-panels = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde.dtsi"
|
||||
@@ -46,6 +46,18 @@
|
||||
qcom,proxy-consumer-enable;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
disp_rdump_memory: disp_rdump_region@0xd5500000 {
|
||||
reg = <0xd5500000 0x00800000>;
|
||||
label = "disp_rdump_region";
|
||||
};
|
||||
};
|
||||
|
||||
&reserved_memory {
|
||||
splash_memory: splash_region {
|
||||
reg = <0x0 0xd5500000 0x0 0x02b00000>;
|
||||
label = "cont_splash_region";
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
@@ -107,7 +119,7 @@
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2 &sde_dp>;
|
||||
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
@@ -139,6 +151,29 @@
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 40 40 720 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 540 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 40 40 720 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
@@ -241,6 +241,9 @@
|
||||
/* offsets are based off dspp 0, 1, 2, and 3 */
|
||||
qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;
|
||||
|
||||
nvmem-cells = <&ssip_config>;
|
||||
nvmem-cell-names = "ssip_config";
|
||||
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
17
display/trustedvm-sun-sde-display-cdp-overlay.dts
Normal file
17
display/trustedvm-sun-sde-display-cdp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-sun-sde.dtsi"
|
||||
#include "trustedvm-sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
143
display/trustedvm-sun-sde-display-cdp.dtsi
Normal file
143
display/trustedvm-sun-sde-display-cdp.dtsi
Normal file
@@ -0,0 +1,143 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
17
display/trustedvm-sun-sde-display-mtp-overlay.dts
Normal file
17
display/trustedvm-sun-sde-display-mtp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-sun-sde.dtsi"
|
||||
#include "trustedvm-sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
69
display/trustedvm-sun-sde-display-mtp.dtsi
Normal file
69
display/trustedvm-sun-sde-display-mtp.dtsi
Normal file
@@ -0,0 +1,69 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-sun-sde-display.dtsi"
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
18
display/trustedvm-sun-sde-display-qrd-overlay.dts
Normal file
18
display/trustedvm-sun-sde-display-qrd-overlay.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-sun-sde.dtsi"
|
||||
#include "trustedvm-sun-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
|
||||
};
|
||||
51
display/trustedvm-sun-sde-display-qrd.dtsi
Normal file
51
display/trustedvm-sun-sde-display-qrd.dtsi
Normal file
@@ -0,0 +1,51 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-sun-sde-display.dtsi"
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
|
||||
};
|
||||
|
||||
28
display/trustedvm-sun-sde-display.dtsi
Normal file
28
display/trustedvm-sun-sde-display.dtsi
Normal file
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display-common.dtsi"
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>,
|
||||
<&clock_cpucc 2>,
|
||||
<&clock_cpucc 3>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>,
|
||||
<&clock_cpucc 2>,
|
||||
<&clock_cpucc 3>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>;
|
||||
};
|
||||
82
display/trustedvm-sun-sde.dtsi
Normal file
82
display/trustedvm-sun-sde.dtsi
Normal file
@@ -0,0 +1,82 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include "sun-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
/* dummy display clock provider */
|
||||
clock_cpucc: qcom,cpucc {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "cpucc_clocks";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x804 0x2>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
reg = <0x0ae00000 0x93800>,
|
||||
<0x0aeb0000 0x2008>,
|
||||
<0x0af80000 0x7000>,
|
||||
<0x0ae44000 0x02c>;
|
||||
|
||||
reg-names = "mdp_phys",
|
||||
"vbif_phys",
|
||||
"regdma_phys",
|
||||
"sid_phys";
|
||||
|
||||
qcom,sde-vm-exclude-reg-names = "sid_phys";
|
||||
|
||||
qcom,sde-hw-version =<0xC0000000>;
|
||||
|
||||
clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
|
||||
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
|
||||
clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
|
||||
"core_clk", "vsync_clk", "lut_clk";
|
||||
qcom,sde-trusted-vm-env;
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
Reference in New Issue
Block a user