From 2f01796505872ef491eda0fea8e0dff5d528e274 Mon Sep 17 00:00:00 2001
From: Sanskar Omar <quic_sansomar@quicinc.com>
Date: Thu, 14 Dec 2023 17:05:29 +0530
Subject: [PATCH 01/14] ARM: dts: msm: introduce AI Scaler support

The Sun platform introduces support for AI Scaler hardware. Update
the device tree definition to provide AI Scaler hardware details
and register access to the MSM DRM driver.

Change-Id: I38944376bc4579759391ff1e70882bf812dc133e
Signed-off-by: Sanskar Omar <quic_sansomar@quicinc.com>
---
 bindings/sde.txt            | 8 ++++++++
 display/sun-sde-common.dtsi | 5 +++++
 2 files changed, 13 insertions(+)

diff --git a/bindings/sde.txt b/bindings/sde.txt
index 2abbe5a5..779a3da7 100644
--- a/bindings/sde.txt
+++ b/bindings/sde.txt
@@ -404,6 +404,12 @@ Optional properties:
 				hardware.
 - qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE
 				wrapper hardware block instance.
+- qcom,sde-dspp-aiqe-aiscaler-off: Array of u32 values indicating the offset of each AIQE
+				AI Scaler block relative to its parent DSPP block.
+- qcom,sde-dspp-aiqe-aiscaler-version: A u32 value indicating the version of the AIQE AI Scaler
+				hardware.
+- qcom,sde-dspp-aiqe-aiscaler-size: A u32 value indicating the shared memory size of each AIQE
+				AI Scaler hardware block instance.
 - qcom,sde-aiqe-has-feature-mdnie:	Boolean property indicating the presence of AIQE feature mDNIe
 				hardware.
 - qcom,sde-aiqe-has-feature-abc:	Boolean property indicating the presence of AIQE feature ABC
@@ -412,6 +418,8 @@ Optional properties:
 				hardware.
 - qcom,sde-aiqe-has-feature-copr:	Boolean property indicating the presence of AIQE feature COPR
 				hardware.
+- qcom,sde-aiqe-has-feature-aiscaler:	Boolean property indicating the presence of AIQE feature
+				AI Scaler hardware.
 - qcom,sde-lm-noise-off:	A u32 value indicating noise layer offset from mixer base.
 - qcom,sde-lm-noise-version:	A u32 value indicating the noise layer version.
 - qcom,sde-vbif-id:		Array of vbif ids corresponding to the
diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi
index c517fc02..eb41ed1e 100644
--- a/display/sun-sde-common.dtsi
+++ b/display/sun-sde-common.dtsi
@@ -205,10 +205,15 @@
 		qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>;
 		qcom,sde-dspp-aiqe-wrapper-size = <0x1c>;
 
+		qcom,sde-dspp-aiqe-aiscaler-off = <0x30000 0xffffffff>;
+		qcom,sde-dspp-aiqe-aiscaler-version = <0x00010000>;
+		qcom,sde-dspp-aiqe-aiscaler-size = <0x7d0>;
+
 		qcom,sde-aiqe-has-feature-mdnie;
 		qcom,sde-aiqe-has-feature-abc;
 		qcom,sde-aiqe-has-feature-ssrc;
 		qcom,sde-aiqe-has-feature-copr;
+		qcom,sde-aiqe-has-feature-aiscaler;
 
 		qcom,sde-lm-noise-off = <0x320>;
 		qcom,sde-lm-noise-version = <0x00010000>;

From 2cc2220b57d32e73c3b02821a22e1a89412923a8 Mon Sep 17 00:00:00 2001
From: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Date: Tue, 12 Dec 2023 13:19:49 -0800
Subject: [PATCH 02/14] ARM: dts: msm: add cont-splash & ramdump support on sun
 target

Add continuous splash memory region & ramdump memory region
on sun target to enable the features.

Change-Id: Ia7bed7b30935a912c977a543430a2b9ad0921439
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
---
 display/sun-sde-display.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi
index d48d6045..c798a37f 100644
--- a/display/sun-sde-display.dtsi
+++ b/display/sun-sde-display.dtsi
@@ -46,6 +46,18 @@
 		qcom,proxy-consumer-enable;
 		pinctrl-names = "default";
 	};
+
+	disp_rdump_memory: disp_rdump_region@0xd5500000 {
+		reg = <0xd5500000 0x00800000>;
+		label = "disp_rdump_region";
+	};
+};
+
+&reserved_memory {
+	splash_memory: splash_region {
+		reg = <0x0 0xd5500000 0x0 0x02b00000>;
+		label = "cont_splash_region";
+	};
 };
 
 &sde_dsi {

From 0cae8dfc8019b5285dee198c24a06a625d4ee463 Mon Sep 17 00:00:00 2001
From: Anjelique Melendez <quic_amelende@quicinc.com>
Date: Thu, 4 Jan 2024 11:56:28 -0800
Subject: [PATCH 03/14] ARM: dts: msm: add display panels under battery_charger
 device for Sun QRD

Add display panels under battery_charger device for Sun so battery_charger
device will receive notifications when display is turned on/off.

Change-Id: Ic128b3285b1ee76469863323f1a69a42ed1c55bd
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
---
 display/sun-sde-display-qrd.dtsi | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi
index 65f8e0d2..9ffcea89 100644
--- a/display/sun-sde-display-qrd.dtsi
+++ b/display/sun-sde-display-qrd.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "sun-sde-display.dtsi"
@@ -57,3 +57,10 @@
 			&dsi_nt37801_amoled_video>;
 	};
 };
+
+&battery_charger {
+	qcom,display-panels = <&dsi_nt37801_amoled_cmd
+				&dsi_nt37801_amoled_cmd_cphy
+				&dsi_nt37801_amoled_video
+				&dsi_nt37801_amoled_video_cphy>;
+};

From 7d485131a1be81a2b1a6d21536d8c9de5a55bfcf Mon Sep 17 00:00:00 2001
From: Ramkumar Radhakrishnan <quic_rradhakr@quicinc.com>
Date: Wed, 22 Nov 2023 02:14:39 -0800
Subject: [PATCH 04/14] ARM: dts: msm: Add trustedvm device tree files for Sun
 target

Add the trusted VM devicetree nodes for Sun target.

Change-Id: I393576e742d0c793d26558e64a3f39102c1de032
Signed-off-by: Ramkumar Radhakrishnan <quic_rradhakr@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
---
 Kbuild                                        |   5 +
 .../trustedvm-sun-sde-display-cdp-overlay.dts |  17 +++
 display/trustedvm-sun-sde-display-cdp.dtsi    | 143 ++++++++++++++++++
 .../trustedvm-sun-sde-display-mtp-overlay.dts |  17 +++
 display/trustedvm-sun-sde-display-mtp.dtsi    |  69 +++++++++
 display/trustedvm-sun-sde-display.dtsi        |  28 ++++
 display/trustedvm-sun-sde.dtsi                |  82 ++++++++++
 7 files changed, 361 insertions(+)
 create mode 100644 display/trustedvm-sun-sde-display-cdp-overlay.dts
 create mode 100644 display/trustedvm-sun-sde-display-cdp.dtsi
 create mode 100644 display/trustedvm-sun-sde-display-mtp-overlay.dts
 create mode 100644 display/trustedvm-sun-sde-display-mtp.dtsi
 create mode 100644 display/trustedvm-sun-sde-display.dtsi
 create mode 100644 display/trustedvm-sun-sde.dtsi

diff --git a/Kbuild b/Kbuild
index e80ba254..a824c4d7 100644
--- a/Kbuild
+++ b/Kbuild
@@ -1,3 +1,4 @@
+ifneq ($(CONFIG_ARCH_QTI_VM), y)
 dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
 		display/sun-sde-display-cdp-overlay.dtbo \
 		display/sun-sde-display-mtp-overlay.dtbo \
@@ -14,6 +15,10 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
 		display/sun-sde-display-mtp-nfc-overlay.dtbo \
 		display/sun-sde-display-cdp-v8-overlay.dtbo \
 		display/sun-sde-display-mtp-v8-overlay.dtbo
+else
+dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
+		display/trustedvm-sun-sde-display-mtp-overlay.dtbo
+endif
 
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
diff --git a/display/trustedvm-sun-sde-display-cdp-overlay.dts b/display/trustedvm-sun-sde-display-cdp-overlay.dts
new file mode 100644
index 00000000..8daf5e96
--- /dev/null
+++ b/display/trustedvm-sun-sde-display-cdp-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "trustedvm-sun-sde.dtsi"
+#include "trustedvm-sun-sde-display-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi
new file mode 100644
index 00000000..26a92cf5
--- /dev/null
+++ b/display/trustedvm-sun-sde-display-cdp.dtsi
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "trustedvm-sun-sde-display.dtsi"
+
+&dsi_vtdr6130_amoled_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
+};
+
+&dsi_vtdr6130_amoled_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
+};
+
+&dsi_vtdr6130_amoled_120hz_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_vtdr6130_amoled_120hz_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sim_panel_au {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_vtdr6130_amoled_qsync_144hz_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_vtdr6130_amoled_qsync_144hz_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
+};
+
+&dsi_sim_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_vid {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_dsc_375_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_dsc_10b_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_dual_sim_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,bl-dsc-cmd-state = "dsi_lp_mode";
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_sec_hd_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
+};
diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts
new file mode 100644
index 00000000..fd2fea89
--- /dev/null
+++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "trustedvm-sun-sde.dtsi"
+#include "trustedvm-sun-sde-display-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi
new file mode 100644
index 00000000..8094ced6
--- /dev/null
+++ b/display/trustedvm-sun-sde-display-mtp.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "trustedvm-sun-sde-display.dtsi"
+
+&dsi_nt37801_amoled_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sim_panel_au {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sim_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_vid {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_dsc_375_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_dsc_10b_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_dual_sim_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,bl-dsc-cmd-state = "dsi_lp_mode";
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_sec_hd_cmd {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
+};
diff --git a/display/trustedvm-sun-sde-display.dtsi b/display/trustedvm-sun-sde-display.dtsi
new file mode 100644
index 00000000..995d7758
--- /dev/null
+++ b/display/trustedvm-sun-sde-display.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sun-sde-display-common.dtsi"
+
+&sde_dsi {
+	clocks = <&clock_cpucc 0>,
+			<&clock_cpucc 1>,
+			<&clock_cpucc 2>,
+			<&clock_cpucc 3>;
+	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
+			"pll_byte_clk1", "pll_dsi_clk1";
+};
+
+&sde_dsi1 {
+	clocks = <&clock_cpucc 0>,
+			<&clock_cpucc 1>,
+			<&clock_cpucc 2>,
+			<&clock_cpucc 3>;
+	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
+			"pll_byte_clk1", "pll_dsi_clk1";
+};
+
+&mdss_mdp {
+	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>;
+};
diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi
new file mode 100644
index 00000000..22855dd8
--- /dev/null
+++ b/display/trustedvm-sun-sde.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,dispcc-sun.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+#include "sun-sde-common.dtsi"
+
+&soc {
+	/* dummy display clock provider */
+	clock_cpucc: qcom,cpucc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "cpucc_clocks";
+		#clock-cells = <1>;
+	};
+
+	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+		compatible = "qcom,smmu_sde_unsec";
+		iommus = <&apps_smmu 0x804 0x2>;
+		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		qcom,iommu-faults = "non-fatal";
+		dma-coherent;
+	};
+};
+
+&mdss_mdp {
+	reg = <0x0ae00000 0x93800>,
+	      <0x0aeb0000 0x2008>,
+	      <0x0af80000 0x7000>,
+	      <0x0ae44000 0x02c>;
+
+	reg-names = "mdp_phys",
+		"vbif_phys",
+		"regdma_phys",
+		"sid_phys";
+
+	qcom,sde-vm-exclude-reg-names = "sid_phys";
+
+	qcom,sde-hw-version =<0xC0000000>;
+
+	clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
+		<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
+	clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
+			"core_clk", "vsync_clk", "lut_clk";
+	qcom,sde-trusted-vm-env;
+};
+
+&mdss_dsi0 {
+	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
+	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+			"pixel_clk", "pixel_clk_rcg", "esc_clk";
+};
+
+&mdss_dsi1 {
+	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
+	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+			"pixel_clk", "pixel_clk_rcg", "esc_clk";
+};
+
+&mdss_dsi_phy0 {
+	qcom,dsi-pll-in-trusted-vm;
+};
+
+&mdss_dsi_phy1 {
+	qcom,dsi-pll-in-trusted-vm;
+};

From c87ac12f64d27946481028513e3072171d7af335 Mon Sep 17 00:00:00 2001
From: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Date: Fri, 19 Jan 2024 17:32:06 -0800
Subject: [PATCH 05/14] ARM: dts: msm: add secure cb to connector-list on sun
 target

Add smmu secure context bank to the connector-list on sun target
to make it as part of the drm component dependent list.

Change-Id: I9e1d65f32b864f12e9683566771acdc687923380
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
---
 display/sun-sde-display.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi
index d48d6045..398e121f 100644
--- a/display/sun-sde-display.dtsi
+++ b/display/sun-sde-display.dtsi
@@ -107,7 +107,7 @@
 };
 
 &mdss_mdp {
-	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2 &sde_dp>;
+	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>;
 };
 
 &dsi_vtdr6130_amoled_cmd {

From b74489855bfe8d6287f55b403d9768331d422ca1 Mon Sep 17 00:00:00 2001
From: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Date: Fri, 19 Jan 2024 13:39:41 +0800
Subject: [PATCH 06/14] ARM: dts: msm: enable esd check on sun target

This change enable esd check on sun target.

Change-Id: I55cbf46247370b31a192b8350a60994d727d48d5
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
---
 display/sun-sde-display-common.dtsi | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi
index 23bce180..54797f5e 100644
--- a/display/sun-sde-display-common.dtsi
+++ b/display/sun-sde-display-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi"
@@ -349,6 +349,12 @@
 &dsi_nt37801_amoled_cmd {
 	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
 	qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
 
 	qcom,mdss-dsi-display-timings {
 		timing@0 {
@@ -369,6 +375,12 @@
 
 &dsi_nt37801_amoled_video_cphy {
 	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
 
 	qcom,mdss-dsi-display-timings {
 		timing@0 {
@@ -382,6 +394,12 @@
 
 &dsi_nt37801_amoled_cmd_cphy {
 	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
 
 	qcom,mdss-dsi-display-timings {
 		timing@0 {
@@ -396,6 +414,12 @@
 &dsi_nt37801_amoled_video {
 	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
 	qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
 
 	qcom,mdss-dsi-display-timings {
 		timing@0 {

From 754cc63fca8f517ee9525b495e12ab2a834553f1 Mon Sep 17 00:00:00 2001
From: Rui Chen <quic_ruc@quicinc.com>
Date: Mon, 22 Jan 2024 10:58:20 +0800
Subject: [PATCH 07/14] ARM: dts: msm: Add trustedvm device tree files for Sun
 qrd

Add the trusted VM devicetree nodes for Sun target.

Change-Id: I5812f991777ed30e4a34f6cf4c4d291c9c850374
Signed-off-by: Rui Chen <quic_ruc@quicinc.com>
---
 Kbuild                                        |  3 +-
 .../trustedvm-sun-sde-display-qrd-overlay.dts | 18 +++++++
 display/trustedvm-sun-sde-display-qrd.dtsi    | 51 +++++++++++++++++++
 3 files changed, 71 insertions(+), 1 deletion(-)
 create mode 100644 display/trustedvm-sun-sde-display-qrd-overlay.dts
 create mode 100644 display/trustedvm-sun-sde-display-qrd.dtsi

diff --git a/Kbuild b/Kbuild
index a824c4d7..93ff5622 100644
--- a/Kbuild
+++ b/Kbuild
@@ -17,7 +17,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
 		display/sun-sde-display-mtp-v8-overlay.dtbo
 else
 dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
-		display/trustedvm-sun-sde-display-mtp-overlay.dtbo
+		display/trustedvm-sun-sde-display-mtp-overlay.dtbo \
+		display/trustedvm-sun-sde-display-qrd-overlay.dtbo
 endif
 
 always-y    := $(dtb-y) $(dtbo-y)
diff --git a/display/trustedvm-sun-sde-display-qrd-overlay.dts b/display/trustedvm-sun-sde-display-qrd-overlay.dts
new file mode 100644
index 00000000..8fac6d6e
--- /dev/null
+++ b/display/trustedvm-sun-sde-display-qrd-overlay.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "trustedvm-sun-sde.dtsi"
+#include "trustedvm-sun-sde-display-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
+			"qcom,qrd";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
+};
diff --git a/display/trustedvm-sun-sde-display-qrd.dtsi b/display/trustedvm-sun-sde-display-qrd.dtsi
new file mode 100644
index 00000000..bee9aabe
--- /dev/null
+++ b/display/trustedvm-sun-sde-display-qrd.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "trustedvm-sun-sde-display.dtsi"
+
+&dsi_nt37801_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_cmd_cphy {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_video_cphy {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
+};
+

From 745316e53e8d59bdffb7b2091c4b28fa2569c5ea Mon Sep 17 00:00:00 2001
From: Christina Oliveira <quic_coliveir@quicinc.com>
Date: Mon, 29 Jan 2024 14:19:45 -0800
Subject: [PATCH 08/14] ARM: dts: msm: add support for ipcc protocol for hw
 fence on sun

This change adds the register address and size for ipcc base and
the dpu client physical id to be used for hw fencing register access.

Change-Id: I6a389626c186cc0f5a10900e890ecd33f6a606d2
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
---
 display/sun-sde-common.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi
index d8fe8840..36d306c0 100644
--- a/display/sun-sde-common.dtsi
+++ b/display/sun-sde-common.dtsi
@@ -12,10 +12,12 @@
 		compatible = "qcom,sde-kms";
 		reg = <0x0ae00000 0x93800>,
 		      <0x0aeb0000 0x2008>,
-		      <0x0af80000 0x7000>;
+		      <0x0af80000 0x7000>,
+		      <0x400000 0x2000>;
 		reg-names = "mdp_phys",
 			"vbif_phys",
-			"regdma_phys";
+			"regdma_phys",
+			"ipcc_reg";
 
 		/* interrupt config */
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -261,6 +263,9 @@
 		qcom,sde-qos-cpu-dma-latency = <300>;
 		qcom,sde-qos-cpu-irq-latency = <300>;
 
+		qcom,sde-ipcc-protocol-id = <0x4>;
+		qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
+
 		/* offsets are relative to "mdp_phys + qcom,sde-off */
 		qcom,sde-reg-dma-off = <0 0x800>;
 		qcom,sde-reg-dma-id = <0 1>;

From f3e72ba454a2d19818c300322c603ce075df2a97 Mon Sep 17 00:00:00 2001
From: Rui Chen <quic_ruc@quicinc.com>
Date: Tue, 30 Jan 2024 13:09:59 +0800
Subject: [PATCH 09/14] ARM: dts: msm: Update trustedvm device tree board id
 for Sun MTP and CDP

Update the trusted VM devicetree for Sun MTP and CDP.

Change-Id: I730350197c25350632bf65adb9aff101685c281d
Signed-off-by: Rui Chen <quic_ruc@quicinc.com>
---
 display/trustedvm-sun-sde-display-cdp-overlay.dts | 2 +-
 display/trustedvm-sun-sde-display-mtp-overlay.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/display/trustedvm-sun-sde-display-cdp-overlay.dts b/display/trustedvm-sun-sde-display-cdp-overlay.dts
index 8daf5e96..757c0dc7 100644
--- a/display/trustedvm-sun-sde-display-cdp-overlay.dts
+++ b/display/trustedvm-sun-sde-display-cdp-overlay.dts
@@ -13,5 +13,5 @@
 	model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
 	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
 	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
-	qcom,board-id = <0x10001 0>;
+	qcom,board-id = <1 0>;
 };
diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts
index fd2fea89..438ebe59 100644
--- a/display/trustedvm-sun-sde-display-mtp-overlay.dts
+++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts
@@ -13,5 +13,5 @@
 	model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
 	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
 	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
-	qcom,board-id = <0x10008 0>;
+	qcom,board-id = <8 0>;
 };

From febcd23b71babca9c5f838a7abdec2f1ca6acc75 Mon Sep 17 00:00:00 2001
From: Christina Oliveira <quic_coliveir@quicinc.com>
Date: Wed, 24 Jan 2024 11:33:00 -0800
Subject: [PATCH 10/14] ARM: dts: msm: add soccp dtsi property to sun target

This change adds the soccp phandle needed for SOCCP power vote for
hw-fencing usecases.

Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
---
 bindings/sde.txt            | 3 +++
 display/sun-sde-common.dtsi | 1 +
 2 files changed, 4 insertions(+)

diff --git a/bindings/sde.txt b/bindings/sde.txt
index 779a3da7..b334b16d 100644
--- a/bindings/sde.txt
+++ b/bindings/sde.txt
@@ -569,6 +569,8 @@ Optional properties:
 					silver or gold or gold+.
 - qcom,sde-qos-cpu-dma-latency:	A u32 value indicating desired PM QoS CPU DMA latency in usec.
 - qcom,sde-qos-cpu-irq-latency:	A u32 value indicating desired PM QoS CPU irq latency in usec.
+- qcom,sde-soccp-controller:    The phandle for the soccp controller.
+				This value is optional and only required for targets with SOCCP.
 - qcom,sde-ipcc-protocol-id:	A u32 value indicating ipcc protocol id used for hw fencing feature.
 - qcom,sde-ipcc-client-dpu-phys-id:	A u32 value indicating ipcc physical client id of dpu used
 					for ipcc registers access.
@@ -911,6 +913,7 @@ Example:
     qcom,sde-qos-cpu-dma-latency = <300>;
     qcom,sde-qos-cpu-irq-latency = <300>;
 
+    qcom,sde-soccp-controller = <&soccp_pas>;
     qcom,sde-ipcc-protocol-id = <0x2>;
     qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
 
diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi
index 36d306c0..5d73da80 100644
--- a/display/sun-sde-common.dtsi
+++ b/display/sun-sde-common.dtsi
@@ -265,6 +265,7 @@
 
 		qcom,sde-ipcc-protocol-id = <0x4>;
 		qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
+		qcom,sde-soccp-controller = <&soccp_pas>;
 
 		/* offsets are relative to "mdp_phys + qcom,sde-off */
 		qcom,sde-reg-dma-off = <0 0x800>;

From 945dccd0fde70ff85699e224ced366f2767de00a Mon Sep 17 00:00:00 2001
From: Christina Oliveira <quic_coliveir@quicinc.com>
Date: Wed, 24 Jan 2024 15:31:57 -0800
Subject: [PATCH 11/14] ARM: dts: msm: add support to configure hw-fence ctl
 reg offset

This change adds support for configuring mdp hw-fence ctl
register offset, as this value can change from target-to-target.

Change-Id: I436bec0732473c21cf4753cb292204ce618de512
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
---
 bindings/sde.txt            | 3 +++
 display/sun-sde-common.dtsi | 1 +
 2 files changed, 4 insertions(+)

diff --git a/bindings/sde.txt b/bindings/sde.txt
index b334b16d..6ceef390 100644
--- a/bindings/sde.txt
+++ b/bindings/sde.txt
@@ -574,6 +574,8 @@ Optional properties:
 - qcom,sde-ipcc-protocol-id:	A u32 value indicating ipcc protocol id used for hw fencing feature.
 - qcom,sde-ipcc-client-dpu-phys-id:	A u32 value indicating ipcc physical client id of dpu used
 					for ipcc registers access.
+- qcom,sde-hw-fence-mdp-ctl-offset:	An optional u32 value indicating the hw fence mdp reg
+					offset.
 - qcom,sde-inline-rot-xin:	An integer array of xin-ids related to inline
 				rotation.
 - qcom,sde-inline-rot-xin-type:	A string array indicating the type of xin,
@@ -916,6 +918,7 @@ Example:
     qcom,sde-soccp-controller = <&soccp_pas>;
     qcom,sde-ipcc-protocol-id = <0x2>;
     qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
+    qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
 
     qcom,sde-vbif-off = <0 0>;
     qcom,sde-vbif-id = <0 1>;
diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi
index 5d73da80..3300a722 100644
--- a/display/sun-sde-common.dtsi
+++ b/display/sun-sde-common.dtsi
@@ -266,6 +266,7 @@
 		qcom,sde-ipcc-protocol-id = <0x4>;
 		qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
 		qcom,sde-soccp-controller = <&soccp_pas>;
+		qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
 
 		/* offsets are relative to "mdp_phys + qcom,sde-off */
 		qcom,sde-reg-dma-off = <0 0x800>;

From 317cfa341d2d4e75ef7d20263f6c7b36e3defdaf Mon Sep 17 00:00:00 2001
From: Jinfeng Gu <quic_gjinfeng@quicinc.com>
Date: Fri, 2 Feb 2024 10:20:02 +0800
Subject: [PATCH 12/14] ARM: dts: msm: enable partial update on sun target

This change enable partial update for cmd mode panel on sun target.

Change-Id: I26eeaca7e8a5a59ca9155f5882c1977c66f4ff23
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
---
 display/sun-sde-display.dtsi | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi
index 398e121f..1797a0be 100644
--- a/display/sun-sde-display.dtsi
+++ b/display/sun-sde-display.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "sun-sde.dtsi"
@@ -139,6 +139,29 @@
 	qcom,ulps-enabled;
 };
 
+&dsi_nt37801_amoled_cmd {
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,partial-update-enabled = "single_roi";
+			qcom,panel-roi-alignment = <720 40 40 40 720 40>;
+		};
+
+		timing@1 {
+			qcom,partial-update-enabled = "single_roi";
+			qcom,panel-roi-alignment = <540 40 40 40 540 40>;
+		};
+	};
+};
+
+&dsi_nt37801_amoled_cmd_cphy {
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,partial-update-enabled = "single_roi";
+			qcom,panel-roi-alignment = <720 40 40 40 720 40>;
+		};
+	};
+};
+
 &dsi_sharp_4k_dsc_cmd {
 	qcom,ulps-enabled;
 };

From 5abba20156978e2d296f2761fbd1b00ea73166d9 Mon Sep 17 00:00:00 2001
From: Kirill Shpin <quic_kshpin@quicinc.com>
Date: Tue, 23 Jan 2024 15:08:34 -0800
Subject: [PATCH 13/14] ARM: dts: msm: add panel configs for MTP and QRD

Adds panel configuration blocks for panels that aren't physically
on Pakala MTP and QRD to their respective device tree files. This
enables using these panels in simulation mode on these devices.

Change-Id: Ic9532583b2371f17879e69869924f86fe181ff93
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
---
 display/sun-sde-display-mtp.dtsi |  86 +++++++++++++++++++-
 display/sun-sde-display-qrd.dtsi | 134 +++++++++++++++++++++++++++++++
 2 files changed, 219 insertions(+), 1 deletion(-)

diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi
index 3154f2e3..b3ebded1 100644
--- a/display/sun-sde-display-mtp.dtsi
+++ b/display/sun-sde-display-mtp.dtsi
@@ -1,10 +1,46 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "sun-sde-display.dtsi"
 
+&dsi_vtdr6130_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
+};
+
+&dsi_vtdr6130_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
+};
+
+&dsi_vtdr6130_amoled_120hz_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
 &dsi_nt37801_amoled_cmd {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -25,6 +61,16 @@
 	qcom,platform-reset-gpio = <&tlmm 98 0>;
 };
 
+&dsi_vtdr6130_amoled_120hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
 &dsi_sim_panel_au {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -35,6 +81,44 @@
 	qcom,platform-reset-gpio = <&tlmm 98 0>;
 };
 
+&dsi_vtdr6130_amoled_qsync_144hz_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_vtdr6130_amoled_qsync_144hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
+};
+
 &dsi_sim_cmd {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi
index 9ffcea89..38786570 100644
--- a/display/sun-sde-display-qrd.dtsi
+++ b/display/sun-sde-display-qrd.dtsi
@@ -5,6 +5,42 @@
 
 #include "sun-sde-display.dtsi"
 
+&dsi_vtdr6130_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
+};
+
+&dsi_vtdr6130_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
+};
+
+&dsi_vtdr6130_amoled_120hz_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
 &dsi_nt37801_amoled_cmd {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -45,6 +81,104 @@
 	qcom,platform-reset-gpio = <&tlmm 98 0>;
 };
 
+&dsi_vtdr6130_amoled_120hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sim_panel_au {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_vtdr6130_amoled_qsync_144hz_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_vtdr6130_amoled_qsync_144hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
+};
+
+&dsi_sim_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_dsc_375_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_dsc_10b_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_dual_sim_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,bl-dsc-cmd-state = "dsi_lp_mode";
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+};
+
+&dsi_sim_sec_hd_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+};
+
 &sde_dsi {
 	qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
 };

From 5468eee8ade549445dd96be7e0ee1a2b57fd93fa Mon Sep 17 00:00:00 2001
From: Ping Li <quic_pingli@quicinc.com>
Date: Fri, 26 Jan 2024 13:18:24 -0800
Subject: [PATCH 14/14] ARM: dts: msm: add entry for ssip fuse configuration

Add dts entry for ssip fuse configuration on Sun platform.

Change-Id: Ia88f0e73d0813c99b7464adc031c4aca8e331440
Signed-off-by: Ping Li <quic_pingli@quicinc.com>
(cherry picked from commit ab7e80ddd8f1e9537e5afe84dbe582061ebb0b01)
---
 bindings/sde.txt     | 5 +++++
 display/sun-sde.dtsi | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/bindings/sde.txt b/bindings/sde.txt
index 6ceef390..68e5ce20 100644
--- a/bindings/sde.txt
+++ b/bindings/sde.txt
@@ -420,6 +420,8 @@ Optional properties:
 				hardware.
 - qcom,sde-aiqe-has-feature-aiscaler:	Boolean property indicating the presence of AIQE feature
 				AI Scaler hardware.
+- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device.
+- nvmem-cell-names: nvmem cell name.
 - qcom,sde-lm-noise-off:	A u32 value indicating noise layer offset from mixer base.
 - qcom,sde-lm-noise-version:	A u32 value indicating the noise layer version.
 - qcom,sde-vbif-id:		Array of vbif ids corresponding to the
@@ -988,6 +990,9 @@ Example:
     qcom,sde-reg-dma-xin-id = <7>;
     qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
 
+    nvmem-cells = <&ssip_config>;
+    nvmem-cell-names = "ssip_config";
+
     qcom,sde-sspp-vig-blocks {
         vcm@0 {
             cell-index = <0>;
diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi
index 18c83c8e..578d63e6 100644
--- a/display/sun-sde.dtsi
+++ b/display/sun-sde.dtsi
@@ -241,6 +241,9 @@
 	/* offsets are based off dspp 0, 1, 2, and 3 */
 	qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;
 
+	nvmem-cells = <&ssip_config>;
+	nvmem-cell-names = "ssip_config";
+
 	qcom,platform-supply-entries {
 		#address-cells = <1>;
 		#size-cells = <0>;