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ARM: dts: msm: Add ipcc_mproc_ns1 for tuna TUIVM

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Add ipcc_mproc_n1 device tree node and entries to enable IPCC and mbox
communication between TUIVM and CDSP SecurePD on tuna TUIVM.

Change-Id: Ia38df4150a766a66cdead3c2dd60b4e6fc2fc4cd
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
This commit is contained in:
Pranav Mahesh Phansalkar
2024-10-24 14:22:49 +05:30
parent b45ae52e3f
commit d35403b3de
1 changed files with 11 additions and 1 deletions
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12
qcom/tuna-vm.dtsi
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@@ -73,7 +73,8 @@
vm-attrs = "context-dump", "crash-restart"; vm-attrs = "context-dump", "crash-restart";
iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>; 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0
0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>;
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
* QUP1_SE4: GPII5 : IRQ_316 * QUP1_SE4: GPII5 : IRQ_316
@@ -324,6 +325,15 @@
<0x17180000 0x200000>; /* GICR * 8 */ <0x17180000 0x200000>; /* GICR * 8 */
}; };
ipcc_mproc_ns1: qcom,ipcc@407000 {
compatible = "qcom,ipcc";
reg = <0x407000 0x1000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
arch_timer: timer { arch_timer: timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
always-on; always-on;