From d35403b3dea4846fc243c9b429ef172ea355fcf3 Mon Sep 17 00:00:00 2001
From: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
Date: Thu, 24 Oct 2024 14:22:49 +0530
Subject: [PATCH] ARM: dts: msm: Add ipcc_mproc_ns1 for tuna TUIVM

Add ipcc_mproc_n1 device tree node and entries to enable IPCC and mbox
communication between TUIVM and CDSP SecurePD on tuna TUIVM.

Change-Id: Ia38df4150a766a66cdead3c2dd60b4e6fc2fc4cd
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
---
 qcom/tuna-vm.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi
index 19fda190..cc4bb9fb 100644
--- a/qcom/tuna-vm.dtsi
+++ b/qcom/tuna-vm.dtsi
@@ -73,7 +73,8 @@
 		vm-attrs = "context-dump", "crash-restart";
 
 		iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
-				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
+				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0
+				0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>;
 
 		/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
 		 * QUP1_SE4: GPII5 : IRQ_316
@@ -324,6 +325,15 @@
 		      <0x17180000 0x200000>;	/* GICR * 8 */
 	};
 
+	ipcc_mproc_ns1: qcom,ipcc@407000 {
+		compatible = "qcom,ipcc";
+		reg = <0x407000 0x1000>;
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		always-on;