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ARM: dts: msm: Update supported frequencies for Sun GPU

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Add intermediate supported power levels for GPU and remove unsupported
power levels from the list.

Change-Id: Ie16c06293dc707561f03aa9f1839a8217f163726
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
This commit is contained in:
Mohammed Mirza Mandayappurath Manzoor
2023-11-20 09:34:44 -08:00
parent 325eb7a028
commit cffcc8cffb
1 changed files with 46 additions and 24 deletions
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70
gpu/sun-gpu-pwrlevels.dtsi
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@@ -15,7 +15,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
qcom,initial-pwrlevel = <9>; qcom,initial-pwrlevel = <11>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>; qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L1 */ /* TURBO_L1 */
@@ -29,20 +29,9 @@
qcom,bus-max = <11>; qcom,bus-max = <11>;
}; };
/* TURBO */ /* NOM_L1 */
qcom,gpu-pwrlevel@1 { qcom,gpu-pwrlevel@1 {
reg = <1>; reg = <1>;
qcom,gpu-freq = <930000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <900000000>; qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -52,8 +41,8 @@
}; };
/* NOM */ /* NOM */
qcom,gpu-pwrlevel@3 { qcom,gpu-pwrlevel@2 {
reg = <3>; reg = <2>;
qcom,gpu-freq = <832000000>; qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -63,8 +52,8 @@
}; };
/* SVS_L2 */ /* SVS_L2 */
qcom,gpu-pwrlevel@4 { qcom,gpu-pwrlevel@3 {
reg = <4>; reg = <3>;
qcom,gpu-freq = <779000000>; qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -74,8 +63,8 @@
}; };
/* SVS_L1 */ /* SVS_L1 */
qcom,gpu-pwrlevel@5 { qcom,gpu-pwrlevel@4 {
reg = <5>; reg = <4>;
qcom,gpu-freq = <734000000>; qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -84,6 +73,17 @@
qcom,bus-max = <10>; qcom,bus-max = <10>;
}; };
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* SVS */ /* SVS */
qcom,gpu-pwrlevel@6 { qcom,gpu-pwrlevel@6 {
reg = <6>; reg = <6>;
@@ -95,9 +95,20 @@
qcom,bus-max = <7>; qcom,bus-max = <7>;
}; };
/* Low_SVS */ /* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 { qcom,gpu-pwrlevel@7 {
reg = <7>; reg = <7>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <443000000>; qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -106,9 +117,20 @@
qcom,bus-max = <6>; qcom,bus-max = <6>;
}; };
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS_D1 */ /* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 { qcom,gpu-pwrlevel@10 {
reg = <8>; reg = <10>;
qcom,gpu-freq = <342000000>; qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -118,8 +140,8 @@
}; };
/* Low_SVS_D2 */ /* Low_SVS_D2 */
qcom,gpu-pwrlevel@9 { qcom,gpu-pwrlevel@11 {
reg = <9>; reg = <11>;
qcom,gpu-freq = <222000000>; qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;