From cffcc8cffb6c415e559f262221d394f68c6971a4 Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Date: Mon, 20 Nov 2023 09:34:44 -0800
Subject: [PATCH] ARM: dts: msm: Update supported frequencies for Sun GPU

Add intermediate supported power levels for GPU and remove unsupported
power levels from the list.

Change-Id: Ie16c06293dc707561f03aa9f1839a8217f163726
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
---
 gpu/sun-gpu-pwrlevels.dtsi | 70 +++++++++++++++++++++++++-------------
 1 file changed, 46 insertions(+), 24 deletions(-)

diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi
index 3699a791..77be73e5 100644
--- a/gpu/sun-gpu-pwrlevels.dtsi
+++ b/gpu/sun-gpu-pwrlevels.dtsi
@@ -15,7 +15,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			qcom,initial-pwrlevel = <9>;
+			qcom,initial-pwrlevel = <11>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
 
 			/* TURBO_L1 */
@@ -29,20 +29,9 @@
 				qcom,bus-max = <11>;
 			};
 
-			/* TURBO */
+			/* NOM_L1 */
 			qcom,gpu-pwrlevel@1 {
 				reg = <1>;
-				qcom,gpu-freq = <930000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
-
-				qcom,bus-freq = <10>;
-				qcom,bus-min = <10>;
-				qcom,bus-max = <11>;
-			};
-
-			/* NOM_L1 */
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
 				qcom,gpu-freq = <900000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
@@ -52,8 +41,8 @@
 			};
 
 			/* NOM */
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
 				qcom,gpu-freq = <832000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
@@ -63,8 +52,8 @@
 			};
 
 			/* SVS_L2 */
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
 				qcom,gpu-freq = <779000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
@@ -74,8 +63,8 @@
 			};
 
 			/* SVS_L1 */
-			qcom,gpu-pwrlevel@5 {
-				reg = <5>;
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
 				qcom,gpu-freq = <734000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
@@ -84,6 +73,17 @@
 				qcom,bus-max = <10>;
 			};
 
+			/* SVS_L0 */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <660000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
 			/* SVS */
 			qcom,gpu-pwrlevel@6 {
 				reg = <6>;
@@ -95,9 +95,20 @@
 				qcom,bus-max = <7>;
 			};
 
-			/* Low_SVS */
+			/* Low_SVS_L1 */
 			qcom,gpu-pwrlevel@7 {
 				reg = <7>;
+				qcom,gpu-freq = <525000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
 				qcom,gpu-freq = <443000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
@@ -106,9 +117,20 @@
 				qcom,bus-max = <6>;
 			};
 
+			/* Low_SVS_D0 */
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <389000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
 			/* Low_SVS_D1 */
-			qcom,gpu-pwrlevel@8 {
-				reg = <8>;
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
 				qcom,gpu-freq = <342000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 
@@ -118,8 +140,8 @@
 			};
 
 			/* Low_SVS_D2 */
-			qcom,gpu-pwrlevel@9 {
-				reg = <9>;
+			qcom,gpu-pwrlevel@11 {
+				reg = <11>;
 				qcom,gpu-freq = <222000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;