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ARM: dts: msm: Add SDCC support for kera

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Add SD Card support for tuna atp, cdp, mtp, rcm and qrd platform.

Change-Id: Iedace83cae3100624b4694845c4747994eb08f80
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
This commit is contained in:
Manish Pandey
2024-11-25 15:06:02 +05:30
parent 9c9b405454
commit c9b972e848
7 changed files with 242 additions and 0 deletions
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21
qcom/kera-atp.dtsi
View File

@@ -2,3 +2,24 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};

21
qcom/kera-cdp.dtsi
View File

@@ -2,6 +2,27 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&qupv3_se8_spi {
#address-cells = <1>;

20
qcom/kera-mtp.dtsi
View File

@@ -9,6 +9,26 @@
#include <dt-bindings/spmi/spmi.h>
#include "pmk8550.dtsi"
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&wcd_usbss {
interrupt-parent = <&spmi_bus>;
interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>;

59
qcom/kera-pinctrl.dtsi
View File

@@ -1920,4 +1920,63 @@
};
};
};
/* sdcc2 pins */
sdc2_on: sdc2_on {
clk {
pins = "gpio62";
function = "SDC2_CLK";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "gpio51";
function = "SDC2_CMD";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "gpio38", "gpio39", "gpio48", "gpio49";
function = "SDC2_DATA";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio58";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_off: sdc2_off {
clk {
pins = "gpio62";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "gpio51";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "gpio38", "gpio39", "gpio48", "gpio49";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
sd-cd {
pins = "gpio58";
bias-pull-up;
drive-strength = <2>;
};
};
};

22
qcom/kera-qrd.dtsi
View File

@@ -2,6 +2,28 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&qupv3_se7_i2c {
status = "ok";
fsa4480: fsa4480@42 {

21
qcom/kera-rcm.dtsi
View File

@@ -2,3 +2,24 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};

78
qcom/kera.dtsi
View File

@@ -57,6 +57,7 @@
aliases: aliases {
serial0 = &qupv3_se13_2uart;
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
mmc1 = &sdhc_2; /* SDC2 SD card slot */
hsuart0 = &qupv3_se5_4uart;
i2c0 = &qupv3_se0_i2c;
i2c1 = &qupv3_se1_i2c;
@@ -2164,6 +2165,83 @@
qcom,client-id = <0x00000001>;
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <160000 100000>;
opp-avg-kBps = <50000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <200000 120000>;
opp-avg-kBps = <104000 0>;
};
};
sdhc_2_dma_resv: sdhc_2_dma_resv_region {
/*
* Restrict IOVA mappings for SDHC2 buffers to the 256 MB region
* from 0x40000000 - 0x4fffffff.
*/
iommu-addresses = <&sdhc_2 0x0 0x40000000>,
<&sdhc_2 0x50000000 0xb0000000>;
};
sdhc_2: sdhci@8804000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <4>;
no-sdio;
no-mmc;
qcom,restore-after-cx-collapse;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
/*
* DLL HSR settings. Refer go/hsr - <Target> DLL settings.
* Note that the DLL_CONFIG_2 value is not passed from the
* device tree, but it is calculated in the driver.
*/
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
0x090106C0 0x80040868>;
iommus = <&apps_smmu 0x540 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
memory-region = <&sdhc_2_dma_resv>;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qos0 {
mask = <0xf8>;
vote = <44>;
};
qos1 {
mask = <0x07>;
vote = <44>;
};
};
ufsphy_mem: ufsphy_mem@1d80000 {
reg = <0x1d80000 0x2000>;
reg-names = "phy_mem";