From c9b972e848b8df42cbe48c0c13e1ad1a27d752b3 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 25 Nov 2024 15:06:02 +0530 Subject: [PATCH] ARM: dts: msm: Add SDCC support for kera Add SD Card support for tuna atp, cdp, mtp, rcm and qrd platform. Change-Id: Iedace83cae3100624b4694845c4747994eb08f80 Signed-off-by: Manish Pandey --- qcom/kera-atp.dtsi | 21 ++++++++++++ qcom/kera-cdp.dtsi | 21 ++++++++++++ qcom/kera-mtp.dtsi | 20 +++++++++++ qcom/kera-pinctrl.dtsi | 59 ++++++++++++++++++++++++++++++++ qcom/kera-qrd.dtsi | 22 ++++++++++++ qcom/kera-rcm.dtsi | 21 ++++++++++++ qcom/kera.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 242 insertions(+) diff --git a/qcom/kera-atp.dtsi b/qcom/kera-atp.dtsi index 9df4770a..fccccc16 100644 --- a/qcom/kera-atp.dtsi +++ b/qcom/kera-atp.dtsi @@ -2,3 +2,24 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; diff --git a/qcom/kera-cdp.dtsi b/qcom/kera-cdp.dtsi index 237c54ed..f9d8f28b 100644 --- a/qcom/kera-cdp.dtsi +++ b/qcom/kera-cdp.dtsi @@ -2,6 +2,27 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; &qupv3_se8_spi { #address-cells = <1>; diff --git a/qcom/kera-mtp.dtsi b/qcom/kera-mtp.dtsi index 33ee45a2..fe3b8f24 100644 --- a/qcom/kera-mtp.dtsi +++ b/qcom/kera-mtp.dtsi @@ -9,6 +9,26 @@ #include #include "pmk8550.dtsi" +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; + &wcd_usbss { interrupt-parent = <&spmi_bus>; interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>; diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi index c2652061..3eef2cd5 100644 --- a/qcom/kera-pinctrl.dtsi +++ b/qcom/kera-pinctrl.dtsi @@ -1920,4 +1920,63 @@ }; }; }; + + /* sdcc2 pins */ + sdc2_on: sdc2_on { + clk { + pins = "gpio62"; + function = "SDC2_CLK"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "gpio51"; + function = "SDC2_CMD"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "gpio38", "gpio39", "gpio48", "gpio49"; + function = "SDC2_DATA"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio58"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "gpio62"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "gpio38", "gpio39", "gpio48", "gpio49"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio58"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; diff --git a/qcom/kera-qrd.dtsi b/qcom/kera-qrd.dtsi index a1af52f3..2aad13e0 100644 --- a/qcom/kera-qrd.dtsi +++ b/qcom/kera-qrd.dtsi @@ -2,6 +2,28 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; + &qupv3_se7_i2c { status = "ok"; fsa4480: fsa4480@42 { diff --git a/qcom/kera-rcm.dtsi b/qcom/kera-rcm.dtsi index 9df4770a..fccccc16 100644 --- a/qcom/kera-rcm.dtsi +++ b/qcom/kera-rcm.dtsi @@ -2,3 +2,24 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 791751e6..65a9b571 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -57,6 +57,7 @@ aliases: aliases { serial0 = &qupv3_se13_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ hsuart0 = &qupv3_se5_4uart; i2c0 = &qupv3_se0_i2c; i2c1 = &qupv3_se1_i2c; @@ -2164,6 +2165,83 @@ qcom,client-id = <0x00000001>; }; + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2_dma_resv: sdhc_2_dma_resv_region { + /* + * Restrict IOVA mappings for SDHC2 buffers to the 256 MB region + * from 0x40000000 - 0x4fffffff. + */ + iommu-addresses = <&sdhc_2 0x0 0x40000000>, + <&sdhc_2 0x50000000 0xb0000000>; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* + * DLL HSR settings. Refer go/hsr - DLL settings. + * Note that the DLL_CONFIG_2 value is not passed from the + * device tree, but it is calculated in the driver. + */ + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 + 0x090106C0 0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + memory-region = <&sdhc_2_dma_resv>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + + qos0 { + mask = <0xf8>; + vote = <44>; + }; + + qos1 { + mask = <0x07>; + vote = <44>; + }; + }; + ufsphy_mem: ufsphy_mem@1d80000 { reg = <0x1d80000 0x2000>; reg-names = "phy_mem";