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ARM: dts: msm: Add SDCC support for kera

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Add SD Card support for tuna atp, cdp, mtp, rcm and qrd platform.

Change-Id: Iedace83cae3100624b4694845c4747994eb08f80
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
This commit is contained in:
Manish Pandey
2024-11-25 15:06:02 +05:30
parent 9c9b405454
commit c9b972e848
7 changed files with 242 additions and 0 deletions
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78
qcom/kera.dtsi
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@@ -57,6 +57,7 @@
aliases: aliases {
serial0 = &qupv3_se13_2uart;
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
mmc1 = &sdhc_2; /* SDC2 SD card slot */
hsuart0 = &qupv3_se5_4uart;
i2c0 = &qupv3_se0_i2c;
i2c1 = &qupv3_se1_i2c;
@@ -2164,6 +2165,83 @@
qcom,client-id = <0x00000001>;
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <160000 100000>;
opp-avg-kBps = <50000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <200000 120000>;
opp-avg-kBps = <104000 0>;
};
};
sdhc_2_dma_resv: sdhc_2_dma_resv_region {
/*
* Restrict IOVA mappings for SDHC2 buffers to the 256 MB region
* from 0x40000000 - 0x4fffffff.
*/
iommu-addresses = <&sdhc_2 0x0 0x40000000>,
<&sdhc_2 0x50000000 0xb0000000>;
};
sdhc_2: sdhci@8804000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <4>;
no-sdio;
no-mmc;
qcom,restore-after-cx-collapse;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
/*
* DLL HSR settings. Refer go/hsr - <Target> DLL settings.
* Note that the DLL_CONFIG_2 value is not passed from the
* device tree, but it is calculated in the driver.
*/
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
0x090106C0 0x80040868>;
iommus = <&apps_smmu 0x540 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
memory-region = <&sdhc_2_dma_resv>;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qos0 {
mask = <0xf8>;
vote = <44>;
};
qos1 {
mask = <0x07>;
vote = <44>;
};
};
ufsphy_mem: ufsphy_mem@1d80000 {
reg = <0x1d80000 0x2000>;
reg-names = "phy_mem";