samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge "ARM: dts: msm: Added interconnects for Tuna"

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QCTECMDR Service
2024-10-18 15:35:05 -07:00
committed by Gerrit - the friendly Code Review server
parent 69b0897d31 632193f30b
commit c94812f7d1
1 changed files with 52 additions and 7 deletions
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59
qcom/tuna-usb.dtsi
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@@ -12,8 +12,8 @@
reg = <0xa600000 0x100000>; reg = <0xa600000 0x100000>;
reg-names = "core_base"; reg-names = "core_base";
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
ranges; ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
@@ -28,23 +28,36 @@
resets = <&gcc GCC_USB30_PRIM_BCR>; resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset"; reset-names = "core_reset";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
interrupt-names = "pwr_event_irq"; <&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
qcom,use-pdc-interrupts;
qcom,use-eusb2-phy;
qcom,core-clk-rate = <200000000>; qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>; qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>; qcom,core-clk-rate-disconnected = <133333333>;
dwc3@a600000 { dwc3_0: dwc3@a600000 {
compatible = "snps,dwc3"; compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>; reg = <0x0 0xa600000 0x0 0xd93c>;
iommus = <&apps_smmu 0x40 0x0>; iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "atomic"; qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; memory-region = <&dwc3_mem_region>;
dma-coherent; dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&eusb2_phy0>, <&usb_nop_phy>;
snps,disable-clk-gating; snps,disable-clk-gating;
snps,has-lpm-erratum; snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>; snps,hird-threshold = /bits/ 8 <0x0>;
@@ -59,4 +72,36 @@
usb-role-switch; usb-role-switch;
}; };
}; };
dwc3_mem_region: dwc3_mem_region {
iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
};
/* USB port related High Speed PHY */
eusb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-snps-eusb2-phy";
reg = <0x88e3000 0x154>,
<0x088e2000 0x4>,
<0x0c278000 0x4>;
reg-names = "eusb2_phy_base",
"eud_enable_reg",
"eud_detect_reg";
vdd-supply = <&L3B>;
qcom,vdd-voltage-level = <0 880000 880000>;
vdd_refgen-supply = <&L2B>;
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB2_CLKREF_EN>;
clock-names = "ref_clk_src", "ref_clk";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
}; };