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ARM: dts: msm: Use upstream smmu addr space prop for qup

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FR92369: Memory team has noticed that buses drivers are using the
legacy "qcom,iommu-dma-addr-pool" DT property and suggested to use
Upstream compatible "iommu-addresses" DT property by this change
there is no impact in functionality.

Change-Id: Ib8b25b2b58ffd12d30672bce3afc75276637c4e1
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
This commit is contained in:
Anil Veshala Veshala
2024-01-31 03:27:54 -08:00
committed by Krishna Chaithanya Reddy G
parent df5683bebe
commit c75e149845
2 changed files with 28 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
qcom/sun-qupv3.dtsi
View File

@@ -23,6 +23,10 @@
* Qup2 7: SE 15
*/
qup1_gpi_iommu_region: qup1_gpi_iommu_region {
iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xFFE00000>;
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
@@ -46,12 +50,16 @@
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x1e>;
qcom,ev-factor = <1>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
memory-region = <&qup1_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "ok";
};
qup1_se_iommu_region: qup1_se_iommu_region {
iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
@@ -62,7 +70,7 @@
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xa3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
memory-region = <&qup1_se_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
@@ -504,6 +512,10 @@
};
};
qup2_gpi_iommu_region: qup2_gpi_iommu_region {
iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xFFE00000>;
};
/* GPI Instance */
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
@@ -527,12 +539,16 @@
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x1e>;
qcom,ev-factor = <1>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
memory-region = <&qup2_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "ok";
};
qup2_se_iommu_region: qup2_se_iommu_region {
iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>;
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
@@ -543,7 +559,7 @@
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x423 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
memory-region = <&qup2_se_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;

9
qcom/sun-vm.dtsi
View File

@@ -483,7 +483,10 @@
* QUP2 : SE7 - Secondary touch
*/
qup_iommu_group: qup_common_iommu_group {
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
<&qupv3_1 0x00000000 0x00020000>,
<&gpi_dma2 0x00000000 0x00020000>,
<&qupv3_2 0x00000000 0x00020000>;
};
/* QUPv3_1 GPI Instance */
@@ -494,6 +497,7 @@
reg-names = "gpi-top";
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -527,6 +531,7 @@
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
@@ -568,6 +573,7 @@
reg-names = "gpi-top";
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
@@ -601,6 +607,7 @@
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";